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| Number | Title | Issue Date |
| 7366931 | Memory modules that receive clock information and are placed in a low power state Embodiments described herein provide a power saving state for a memory system. For example, a memory system may derive clocking information from a training pattern sent over a memory channel. A memory may comprise a link to receive training frames, and circuitry to ... | 04/29/2008 |
| 7353316 | System and method for re-routing signals between memory system components A plurality of memory modules used in a computer system each include a memory hub that is connected to a plurality of memory devices. The memory modules are connected to each other in series so that signals are coupled between the memory modules and the memory hub c... | 04/01/2008 |
| 7348219 | Method of mounting memory device on PCB for memory module A memory module and a method of mounting memory devices on a PCB to form the memory module substantially reduce unnecessary routing space and improve signal attenuation characteristics. In the method of mounting and sequentially connecting at least two memory device... | 03/25/2008 |
| 7323733 | Nonvolatile memory and fabrication method thereof A nonvolatile memory and a fabrication method thereof. The nonvolatile memory includes a substrate, a bottom electrode deposited on the substrate, a resistor layer deposited on the bottom electrode, and a top electrode on the resistor layer. The bottom electrode inc... | 01/29/2008 |
| 7310458 | Stacked module systems and methods The present invention provides methods for constructing stacked circuit modules and precursor assemblies with flexible circuitry. Using the methods of the present invention, a single set of flexible circuitry whether articulated as one or two flex circuits may be em... | 12/18/2007 |
| 7302518 | Method and system for managing a suspend request in a flash memory System and method for the managing of suspend requests in flash memory devices. The system includes a microcontroller performing a modify operation on a flash memory array, a memory coupled to the microcontroller and storing suspend sequence code for causing a suspe... | 11/27/2007 |
| 7270557 | High-density storage device A high-density storage device has a housing and a memory and controller assembly. The housing has a plug part and a socket part receiving the plug part of other high-density storage device. The memory and controller assembly is mounted in the housing and has a circu... | 09/18/2007 |
| 7259745 | Method for driving electrophoresis display apparatus A method for driving a display apparatus having display memory property is provided. In the method, the display apparatus includes an electrode group composed of at least a first electrode and a second electrode. The method includes the steps of: applying a voltage ... | 08/21/2007 |
| 7251157 | Semiconductor device Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory... | 07/31/2007 |
| 7251153 | Memory A memory capable of suppressing disturbance causing disappearance of data from a nonselected memory cell is provided. This memory applies a second voltage of polarity reverse to that of a first voltage applied to a nonselected memory cell in a read operation to at l... | 07/31/2007 |
| 7212424 | Double-high DIMM with dual registers and related methods One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressi... | 05/01/2007 |
| 7200031 | Proton and heavy ion SEU resistant SRAM A method and system is disclosed for reducing proton and heavy ion SEU sensitivity of a static random access memory (SRAM) cell. A first passive delay element has been inserted in series with an active delay element in a first feedback path of the SRAM cell, and a s... | 04/03/2007 |
| 7200787 | Memory channel utilizing permuting status patterns Memory apparatus and methods utilize permuting status patterns. A memory agent may include a pattern generator capable of generating permuting status patterns. A system may include first and second memory agents that send data and permuting status patterns over the ... | 04/03/2007 |
| 7183012 | Structure having pores, magnetic recording medium, and method of manufacturing same The invention provides a magnetic recording medium and a method of manufacturing the magnetic recording medium, in which a high density and good storage stability can be achieved by giving anisotropy in shape to a magnetic substance. A plan shape of the magnetic sub... | 02/27/2007 |
| 7179690 | High reliability triple redundant latch with voting logic on each storage node In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three v... | 02/20/2007 |
| 7147942 | Perpendicular magnetic recording medium and method of manufacturing the same and product thereof The quantity of oxide contained in a magnetic layer is controlled to control the crystal grains and the segregation structure for ensuring low noise characteristic in a granular magnetic layer of a perpendicular magnetic recording medium. The granular magnetic layer... | 12/12/2006 |
| 7139193 | Non-volatile memory with two adjacent memory cells sharing same word line A nonvolatile semiconductor memory device having a small layout size includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The memory cell array includes a plurality of element isolation regions. Ea... | 11/21/2006 |
| 7136315 | Bank selectable parallel test circuit and parallel test method thereof A parallel test circuit performs a selective test on a specific bank. The bank selectable parallel test circuit comprises a bank selecting control unit and a plurality of bank selecting units. The bank selecting control unit outputs a test mode control signal for se... | 11/14/2006 |
| 7116579 | Semiconductor storage device and mobile electronic apparatus A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for performing a sequence of a program or erase operation with respect to the memory array, a decoder for decoding a signal indicating a curr... | 10/03/2006 |
| 7110297 | Semiconductor storage device and mobile electronic apparatus A semiconductor storage device is provided, which comprises a memory array comprising memory elements. Each memory element comprises a gate electrode, a channel region, first and second diffusion regions, and first and second memory function sections provided an opp... | 09/19/2006 |
| 7087950 | Flash memory cell, flash memory device and manufacturing method thereof The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said ch... | 08/08/2006 |
| 7087952 | Dual function FinFET, finmemory and method of manufacture A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating ... | 08/08/2006 |
| 7081784 | Data output circuit of memory device A data output circuit of a memory device comprises an output enable signal generating unit, an output driving unit, an output driving unit and an output enable control unit. The output enable signal generating unit generates a reference output enable signal in respo... | 07/25/2006 |
| 7067206 | Perpendicular magnetic recording medium and a method of manufacturing the same A perpendicular magnetic recording medium has a granular magnetic layer and a nonmagnetic underlayer of a metal or an alloy having a hexagonal close packed (hcp) crystal structure. A seed layer of a metal or an alloy of a face-centered cubic (fcc) crystal structure ... | 06/27/2006 |
| 6989536 | Electron-beam writing device and electron-beam writing method The present invention aims at providing a device and method for writing a line with a high degree of precision at high speed. Distance calculation means 311 calculates the start-to-end point distance L of a writing pattern (S502), and number-of-scan-cl... | 01/24/2006 |
| 6985381 | System and method for reading magnetization orientation of MRAM cells A method for reading the magnetization orientation of a memory cell includes applying a magnetic field to the memory cell, observing any change in resistance of the memory cell as the magnetic field is applied, and determining the magnetization orientation based upo... | 01/10/2006 |
| 6958934 | Method of programming and erasing multi-level flash memory A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards t... | 10/25/2005 |
| 6917549 | Integrated memory and method for operating it An integrated memory has a memory cell array having word lines and bit lines. The bit lines are organized in bit line pairs. The bit lines of the bit line pairs cross one another at a crossing location and run parallel to one another. A sense amplifier is connected ... | 07/12/2005 |
| 6905897 | Wafer acceptance testing method and structure of a test key used in the method A wafer acceptance testing method for monitoring GC-DT misalignment and a test key structure are disclosed. The test key includes a deep trench capacitor structure biased to a first voltage (VDT). The deep trench capacitor structure includes a buried stra... | 06/14/2005 |
| 6903983 | Semiconductor integrated circuit device and read start trigger signal generating method therefor A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses an... | 06/07/2005 |
| 6856562 | Test structure for measuring a junction resistance in a DRAM memory cell array A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array where the active regions of the selection transistors are in rows in a first direction and... | 02/15/2005 |
| 6795354 | Circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof A circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof are provided. The AC-timing parameter control circuit includes a delay-time-defining portion, a comparing portion, and a controlling portion. The control circuit com... | 09/21/2004 |
| 6791868 | Ferromagnetic resonance switching for magnetic random access memory A new method of performing the write operation on the MRAM bit cell with improved switching selectivity and lower write current requirements is achieved utilizing oscillating word write currents at frequency near the ferromagnetic resonance frequency of the free lay... | 09/14/2004 |
| 6392919 | Reduction of imprint in ferroelectric devices using a depoling technique A method for reducing imprint in a ferroelectric device which includes the steps of: applying a signal having a bipolar pulse shape for a predetermined time to the ferroelectric device; and decreasing the signal amplitude gradually in predetermined interv... | 05/21/2002 |
| 6337815 | Semiconductor memory device having redundant circuit A semiconductor memory device includes word lines, normal bit lines, a redundant bit line, and normal memory cells for storing data and each of which is coupled to one of the word lines and to one of the normal bit lines. The device also includes redundan... | 01/08/2002 |
| 4785199 | Programmable complementary transistors Programmable logic gate structures employ pairs of complementary transistors. Programming of the transistors is accomplished either by voltage biasing a shared floating gate of a CMOS transistor pair or by providing a variable resistance serially or in pa... | 11/15/1988 |
| 4384346 | Thin film magneto-resistive apparatus for effecting readout from magnetic memory devices The present invention provides thin film magneto-resistive readout apparatus for providing readout from magnetic memory devices such as magnetic tapes, the apparatus comprising a thin film magneto-resistive readout head element, a narrow pulse generator f... | 05/17/1983 |
| 4128901 | Ground-reference power supply for gas discharge display/memory panel driving and addressing circuitry A ground-reference addressing power supply is connected to the driving and addressing circuitry of a gas discharge display/memory panel for generating write and erase pulse voltages. The addressing power supply is referenced to the same ground potential a... | 12/05/1978 |
| 4032904 | Means for refreshing AC stable storage cells A refresh circuit for AC stable storage cells utilizing an asymmetric a stable power source for controlling an auxiliary shift register which in turn controls the refreshing shift register. The outputs of the refreshing shift register are coupled to the g... | 06/28/1977 |
| 4031525 | Process for recording and reproduction of information in electromagnetic form A process for the storage and retrieval of information in electromagnetic form from an information carrier, made of ferromagnetic, ferrimagnetic, antiferrimagnetic, metamagnetic ferroelectric or antiferroelectric material. An information carrier builds up... | 06/21/1977 |
