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| Number | Title | Issue Date |
| 8111565 | Memory interface and operation method of it A memory interface includes a first delaying circuit configured to delay write data to be supplied to an input buffer; a second delaying circuit configured to delay read data read out from an output buffer; a data write circuit configured to supply said write data t... | 02/07/2012 |
| 8098535 | Method and apparatus for gate training in memory interfaces An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. ... | 01/17/2012 |
| 8094506 | Method and apparatus for timing adjustment A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system... | 01/10/2012 |
| 8089820 | Semiconductor integrated circuit and method thereof A semiconductor IC device which includes a common column signal generating block and a column strobe signal generating block. The common signal generating block can provide precolumn strobe signals by using external command signals and a first group of bank addresse... | 01/03/2012 |
| 8085608 | Signal adjusting system and signal adjusting method A signal adjusting system includes: a signal generating apparatus for transmitting a first driving signal and a second driving signal, a plurality of signal transmitting paths coupled to the signal generating apparatus, and a controlling apparatus coupled to the plu... | 12/27/2011 |
| 8072826 | Memory control circuit and memory control method A memory control circuit includes a data sample circuit, a first delay control circuit, a second delay control circuit and a data circuit. The data sample circuit is used for generating a first data strobe signal and a second data strobe signal. The first delay cont... | 12/06/2011 |
| 8054700 | Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device A semiconductor memory device operates in synchronization with a system clock, without using a synchronous circuit such as a DLL or a PLL. The semiconductor memory device includes a synchronous circuit for generating output signals phase aligned with the system cloc... | 11/08/2011 |
| 8050118 | Semiconductor memory device A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signa... | 11/01/2011 |
| 8031553 | Data strobe signal generating device and a semiconductor memory apparatus using the same A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first clock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled, a... | 10/04/2011 |
| 8027210 | Data input apparatus with improved setup/hold window In the data input apparatus, a data delay unit outputs data input from outside the data input apparatice. The data delay unit varies the degree of delay in response to a test mode signal. A data alignment signal generating unit receives a first signal synchronized w... | 09/27/2011 |
| 8023342 | Preamble detection and postamble closure for a memory interface controller A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control... | 09/20/2011 |
| 8014218 | Capacitively isolated mismatch compensated sense amplifier According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifie... | 09/06/2011 |
| 8009491 | Memory access strobe configuration system and process A memory access strobe configuration system and process operable to generate a strobe signal having a selected phase. Based on the strobe signal, a write/read cycle using a first logic value at a memory location of a memory device generates a result logic value. The... | 08/30/2011 |
| 8009490 | Memory interface circuit and memory system including the same The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave delay unit selects one signal of an inversion signal of the clock si... | 08/30/2011 |
| 8009492 | Circuit for generating data strobe signal and method A circuit for generating a data strobe signal includes: a control signal generation unit configured to generate a strobe control signal defining an activation time period where a first data strobe signal and a second data strobe signal, which is an inverted signal o... | 08/30/2011 |
| 8004911 | Memory system, memory device, and output data strobe signal generating method An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip... | 08/23/2011 |
| 7990783 | Postamble timing for DDR memories Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their fron... | 08/02/2011 |
| 7990782 | Data strobe signal noise protection apparatus and semiconductor integrated circuit A data strobe signal noise prevention apparatus and semiconductor integrated circuit includes a transition protection unit configured to protect a transition of a data strobe signal in response to a control signal and a controller configured to determine when a burs... | 08/02/2011 |
| 7990781 | Write strobe generation for a memory interface controller A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data genera... | 08/02/2011 |
| 7983112 | Semiconductor device which transmits or receives a signal to or from an external memory by a DDR system A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a tran... | 07/19/2011 |
| 7983094 | PVT compensated auto-calibration scheme for DDR3 Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. ... | 07/19/2011 |
| 7983100 | Method for generating read enable signal and memory system using the method A method for generating a read enable signal which is for controlling reading of a pair of data strobe signals and a data signal in a memory system is provided. The method comprises: detecting whether the pair of data strobe signals are both high or low; and generat... | 07/19/2011 |
| 7983101 | Circuit for generating data strobe signal in DDR memory device and method therefor The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe si... | 07/19/2011 |
| 7978546 | Memory controller, PCB, computer system and memory adjusting method adjusting a memory output signal characteristic A memory controller, a PCB and a computer system employing the memory controller, and a memory adjusting method using the memory controller. The memory controller interfaces data reading from and writing to a memory and includes: a characteristic estimating part est... | 07/12/2011 |
| 7974143 | Memory system, a memory device, a memory controller and method thereof The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic lev... | 07/05/2011 |
| 7969801 | Data input circuit and nonvolatile memory device including the same A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe signal and output the external data as first internal data in respons... | 06/28/2011 |
| 7961533 | Method and apparatus for implementing write levelization in memory subsystems Methods and apparatus for aligning a clock signal and a set of strobe signals are disclosed. In one embodiment, a memory controller includes a clock generator configured to generate the clock signal, and a respective strobe signal generator configured to generate ea... | 06/14/2011 |
| 7961534 | Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a s... | 06/14/2011 |
| 7957218 | Memory controller with skew control and method A dual data rate (DDR) memory controller and method are provided. The method includes: receiving a first data strobe at a first terminal from a first memory having a first rank; receiving a first data signal at a second terminal from the first memory having the firs... | 06/07/2011 |
| 7952957 | Circuit for generating read and signal and circuit for generating internal clock using the same A circuit for generating a read end signal includes a clock transferring unit which receives a clock signal, a write/read status signal and an all bank precharge signal and outputs a delayed clock signal, a read signal detecting unit which receives a read pulse sign... | 05/31/2011 |
| 7944761 | Memory device having strobe terminals with multiple functions A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information ... | 05/17/2011 |
| 7916559 | Semiconductor memory device and operation method thereof There is provided a semiconductor memory device including: a source strobe signal generating unit configured to generate a source strobe signal having a first or a second activation width corresponding to a normal mode and a bank grouping mode; a final strobe signal... | 03/29/2011 |
| 7916575 | Configurable latching for asynchronous memories A memory, such as a flash memory, may receive a configuration bit from a memory controller to set the memory in one of two selectable modes. Thus, based on the way the memory controller operates, it can adapt the operation of the memory to suit the memory controller... | 03/29/2011 |
| 7911857 | Preamble detection and postamble closure for a memory interface controller A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control... | 03/22/2011 |
| 7907471 | Memory control circuit and semiconductor integrated circuit incorporating the same A memory control circuit includes a clock generation circuit that generates a clock signal and provides the clock signal to an external memory device, and at least one retention circuit that retains a data signal provided from the external memory device only under a... | 03/15/2011 |
| 7907472 | Semiconductor integrated circuit for fetching read data from a DDR-SDRAM operating in synchronization with a clock A semiconductor integrated circuit (100) fetches read data from DDR-SDRAMs (110, 120) each operating in synchronization with a clock, and transfers the read data. The semiconductor integrated circuit (100) includes read buffers (104, 105)... | 03/15/2011 |
| 7889579 | Using differential data strobes in non-differential mode to enhance data capture window A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether these skews arise from reference voltage variation, data pattern loa... | 02/15/2011 |
| 7889580 | Memory system having incorrupted strobe signals A memory system circuit and method therefor are disclosed. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having... | 02/15/2011 |
| 7889578 | Single-strobe operation of memory devices An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe ... | 02/15/2011 |
| 7885127 | Semiconductor memory device and operation method thereof A semiconductor memory device includes a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal and a column command signal, and a main strobe signal generator config... | 02/08/2011 |
