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| Number | Title | Issue Date |
| 7675793 | Semiconductor memory device and driving method for the device This disclosure concerns a semiconductor memory device comprising: memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a bit line pair connected to the memory cells and transmitting data stored in the memory cells;... | 03/09/2010 |
| 7663941 | Semiconductor memory device This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a pair of bit lines connected to the memory cells, and transmitting data of the memory cells; a ... | 02/16/2010 |
| 7663940 | Semiconductor memory device and driving method thereof A semiconductor memory device is capable of reducing the current dissipation in a termination circuit and allowing a voltage level of a GIO line to rapidly reach a voltage level of a termination voltage when a termination operation is performed. The semiconductor me... | 02/16/2010 |
| 7663939 | Voltage stabilizer memory module A memory module is disclosed. The memory module comprises a voltage supply; a memory interface coupled to the voltage supply; a plurality of memory components; and a voltage stabilizer converter (VSC) coupled to the memory interface and to the plurality of memory co... | 02/16/2010 |
| 7643358 | Non volatile semiconductor memory device A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage... | 01/05/2010 |
| 7639550 | Semiconductor memory device with bi-directional read and write data transport A semiconductor memory device includes a pair of local input/output (IO) lines, a global IO line, a local driver configured to pull up/down voltage levels of the first and second local IO lines in response to input data, a global driver configured to pull up/down a ... | 12/29/2009 |
| 7639549 | Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port... | 12/29/2009 |
| 7633815 | Flexible word line boosting across VCC supply Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting cap... | 12/15/2009 |
| 7623408 | Semiconductor memory device comprising data path controller and related method A semiconductor memory device and a related method are disclosed. The semiconductor memory device includes a data sensing output unit simultaneously providing first and second data to first and second data path lines, respectively; and a data output circuit, wherein... | 11/24/2009 |
| 7616507 | Microprocessor boot-up controller, nonvolatile memory controller, and information processing system A memory system including a nonvolatile semiconductor memory device and a controller. The memory device includes a plurality of word lines; and a plurality of memory cells each connected to a corresponding one of the word lines and each having N threshold voltages f... | 11/10/2009 |
| 7602654 | Semiconductor memory device comprising a plurality of static memory cells A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lower... | 10/13/2009 |
| 7599231 | Adaptive regulator for idle state in a charge pump circuit of a memory device An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduc... | 10/06/2009 |
| 7570525 | Semiconductor memory device with adjustable selected work line potential under low voltage condition A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and tran... | 08/04/2009 |
| 7561480 | Ground biased bitline register file In general, in one aspect, the disclosure describes an apparatus including a memory cell. Ground biased write control circuitry is used to bias write and writebar bitlines when the memory cell is not performing a write operation. Ground biased read control circuitry... | 07/14/2009 |
| 7554863 | Voltage control circuit and semiconductor device having the voltage control circuit A voltage control circuit of the present invention is applicable to a combination of a decoder circuit and a level conversion circuit connected to the decoder circuit. The voltage control circuit includes a level conversion circuit voltage line for applying a voltag... | 06/30/2009 |
| 7551497 | Memory circuits preventing false programming Memory circuits capable of preventing false programming caused by power-up sequence are provided, in which a programmable unit comprises a plurality of programmable elements, a source bus coupled between an external programming voltage and the programmable elements,... | 06/23/2009 |
| 7548469 | Circuit and method of generating a boosted voltage in a semiconductor memory device A circuit generates a boosted voltage in a semiconductor memory device, where the semiconductor memory device includes a memory cell array having a plurality of non-edge sub-arrays and at least one edge sub-array. The circuit includes a plurality of boosted voltage ... | 06/16/2009 |
| 7548468 | Semiconductor memory and operation method for same A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge op... | 06/16/2009 |
| 7545685 | High voltage switch circuit having boosting circuit and flash memory device including the same A high-voltage switch circuit includes an enable control circuit, a feedback circuit, a boosting circuit, and a high voltage switch. The enable control circuit precharges an output node to a set voltage in response to an enable signal. The feedback circuit supplies ... | 06/09/2009 |
| 7525853 | Semiconductor device and method for boosting word line A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When ... | 04/28/2009 |
| 7492647 | Voltage generation circuit and semiconductor memory device including the same A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and... | 02/17/2009 |
| 7489566 | High voltage generator and related flash memory device A high voltage generator includes a charge pump generating a high voltage in response to a pumping clock signal, a charge/discharge circuit responsive to the pumping clock signal and charging the high voltage to generate an output voltage, a comparator for comparing... | 02/10/2009 |
| 7480192 | Pull-up voltage circuit A pull-up voltage circuit and method for reducing power consumption therewith are described. A pull-up voltage circuit has an inverter powered by a first supply voltage. A first p-type transistor and an n-type transistor are commonly gated to receive output from a f... | 01/20/2009 |
| 7480191 | High speed logic level shifter A circuit for transmitting logic signals across a high voltage barrier has a logic signal buffer with true and complement state differential outputs. A binary flip-flop with set and reset inputs is further provided. A first coupling capacitor is coupled to the true ... | 01/20/2009 |
| 7474570 | Semiconductor device A semiconductor device capable of improving the accuracy determines whether a prescribed input potential is higher or lower than a reference potential. This semiconductor device comprises first capacitance unit and second capacitance unit having different ON- and OF... | 01/06/2009 |
| 7474571 | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and wri... | 01/06/2009 |
| 7468923 | Semiconductor integrated circuit There is provided a semiconductor integrated circuit including a logic circuit and a writing circuit configured to receive a writing data outputted from the logic circuit, invert the writing data to generate an inverted data, compare the writing data with the invert... | 12/23/2008 |
| 7466605 | Semiconductor device and control method therefor A non-volatile semiconductor device provides a pull-up transistor (M1) for a word line drive which can be downsized. The semiconductor device includes a first decoder (109) including a pull-up transistor (M1) selecting and driving a word line (P... | 12/16/2008 |
| 7447085 | Multilevel driver The present disclosure includes various method, device, and system embodiments for multilevel driving of rowlines and/or wordlines. One such method embodiment includes supplying a first power voltage (V1) and a second power voltage (V2) that is greater... | 11/04/2008 |
| 7443740 | Integrated semiconductor memory with adjustable internal voltage An integrated semiconductor memory includes a clock generator circuit for generating an internal clock signal that exhibits a certain phase angle with respect to an external clock signal. The phase angle is dependent on a value of the supply voltage of the clock gen... | 10/28/2008 |
| 7443706 | High-performance memory and related method In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory... | 10/28/2008 |
| 7440340 | Output buffer of a semiconductor memory device A data output buffer includes an output terminal, a buffer and a pull-down driver. The output terminal is coupled to a first end of a transmission line, the transmission line being coupled to a pull-up termination resistor at a second end. The buffer pulls up the ou... | 10/21/2008 |
| 7440343 | Output driving device An output driving device includes a pull-up driver for pull-up driving an output node in response to a pull-up control signal; a pull-down driver for pull-down driving the output node in response to a pull-down control signal; and a first n-type metal oxide semicond... | 10/21/2008 |
| 7440344 | Level shifter for low voltage operation A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control o... | 10/21/2008 |
| 7441072 | Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write d... | 10/21/2008 |
| 7440354 | Memory with level shifting word line driver and method thereof A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory ... | 10/21/2008 |
| 7436696 | Read-preferred SRAM cell design A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled t... | 10/14/2008 |
| 7423911 | Bit line control circuit for semiconductor memory device A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an o... | 09/09/2008 |
| 7417528 | RFID device having nonvolatile ferroelectric memory device A RFID device has a nonvolatile ferroelectric memory including a memory cell array area supplied only with a high voltage and a peripheral area supplied with a low voltage, thereby reducing power consumption. The RFID device includes an antenna adapted and configure... | 08/26/2008 |
| 7417910 | Low voltage semiconductor memory device A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; a reference cell block including ... | 08/26/2008 |