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| Number | Title | Issue Date |
| 8130560 | Multi-rank partial width memory modules A system is provided for multi-rank, partial-width memory modules. A memory controller is provided. Additionally, a memory bus is provided. Further, a memory module with a plurality of ranks of memory circuits is provided, the memory module including a first number ... | 03/06/2012 |
| 8116144 | Memory module having a memory device configurable to different data pin configurations A memory module includes a memory device having a plurality of data pins and conductive lines electrically connected to the plurality of data pins. The memory device is configurable, using at least one input to the memory device, to a data pin configuration selected... | 02/14/2012 |
| 8064268 | Method and system for a serial peripheral interface An integrated circuit device includes a serial peripheral interface adapted for receiving a first command supporting an address of a first configuration, wherein the serial peripheral interface supports an address of a second configuration upon receipt of a second c... | 11/22/2011 |
| 8014212 | Semiconductor device and control method thereof Disclosed is a memory circuit that includes a plurality of columns of bit line pairs, each bit line pair including True and Bar bit lines, between which at least a memory cell is connected; a sense amplifier that has True and Bar terminals and that performs differen... | 09/06/2011 |
| 7957202 | Semiconductor device and method of controlling the same A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable ... | 06/07/2011 |
| 7920431 | Asynchronous/synchronous interface The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at le... | 04/05/2011 |
| 7894274 | Memories with improved write current A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit co... | 02/22/2011 |
| 7859915 | Semiconductor device and method of controlling the same A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable ... | 12/28/2010 |
| 7804720 | Integrated circuit memory devices including mode registers set using a data input/output bus An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data wri... | 09/28/2010 |
| 7684258 | Semiconductor memory and controller with time-shared mode for row address, column address and data mask signals inputted via address terminals To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data ... | 03/23/2010 |
| 7679969 | Semiconductor memory device utilizing data mask signal for sharing an input/output channel in a test mode and data output method using the same A semiconductor device receives a first data mask signal and a second data mask signal. A data mask control unit outputs a data mask control signal by combining a test mode signal with the first data mask signal. A data clock output unit receives a delay locked loop... | 03/16/2010 |
| 7675794 | Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuit A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit inc... | 03/09/2010 |
| 7675790 | Over driving pin function selection method and circuit A novel method and circuit are disclosed for providing an alternate function to a semiconductor device having a normal operating voltage range and an input pin for receiving an input signal of a voltage level within a normal signal voltage range, for selecting an al... | 03/09/2010 |
| 7636261 | Semiconductor memory device capable of high-speed cache read operation Primary data caches are connected to a common signal line, and secondary data caches are connected to an I/O data line. While data in the secondary data cache is being output to the I/O data line, the common signal line is used to make determinations for data in fla... | 12/22/2009 |
| 7616504 | High speed array pipeline architecture A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output ... | 11/10/2009 |
| 7593271 | Memory device including multiplexed inputs Systems and methods are described for reducing the number of exterior contacts on a semiconductor package without reducing the number of address, data and control signals used by an integrated circuit interior to the semiconductor package. In some embodiments, two s... | 09/22/2009 |
| 7570522 | Semiconductor memory device, semiconductor device, and data write method A semiconductor memory device includes an output buffer which outputs an enable signal which makes an external memory device operable, an address buffer which generates an address at which data is held in the external memory device, an input buffer which receives th... | 08/04/2009 |
| 7457170 | Memory device that provides test results to multiple output pads A memory device including at least two output pads and at least two memory die. Each of the at least two memory die is configured to provide an output signal that includes compressed test results to any of the at least two output pads. ... | 11/25/2008 |
| 7447109 | Semiconductor storage device Disclosed is a semiconductor storage device which has a shared address/data terminal that shares an address terminal and a data terminal. In a latency period extending from receipt of an access command to a cell array to input or output of data, which corresponds to... | 11/04/2008 |
| 7440337 | Nonvolatile semiconductor memory apparatus having buffer memory for storing a program and buffering work data A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit ( | 10/21/2008 |
| 7440336 | Memory device having terminals for transferring multiple types of data A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output au... | 10/21/2008 |
| 7437500 | Configurable high-speed memory interface subsystem A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic rando... | 10/14/2008 |
| 7417901 | Memory device having terminals for transferring multiple types of data A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output ... | 08/26/2008 |
| 7417888 | Method and apparatus for resetable memory and design approach for same A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupl... | 08/26/2008 |
| 7405980 | Shared terminal memory interface A memory architecture for a disk drive system in which Synchronous Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two me... | 07/29/2008 |
| 7403437 | ROM test method and ROM test circuit The present invention provides a ROM test circuit capable of shortening a test time and a test method therefor. When data written into a plurality of ROMs are tested, data of the ROM(1) and ROM(2) are selected based on the output data of the specific R... | 07/22/2008 |
| 7400539 | Memory device having terminals for transferring multiple types of data A device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxilia... | 07/15/2008 |
| 7366032 | Multi-ported register cell with randomly accessible history A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality... | 04/29/2008 |
| 7366860 | Storage device configured to sequentially input a command A storage device is capable of sequentially inputting a command, which includes address information and attached information, from an information processor through an input/output unit. The storage device includes a storage unit for storing data; an extractor for ex... | 04/29/2008 |
| 7362622 | System for determining a reference level and evaluating a signal on the basis of the reference level A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level. ... | 04/22/2008 |
| 7363427 | Memory controller connection to RAM using buffer interface A memory subsystem controller and buffer for a computer and a second buffer for memory tag operations. The buffers are linked to the memory controller by two bidirectional data busses. The controller operates the memory subsystem by passing memory addresses to the m... | 04/22/2008 |
| 7359173 | System and method for protecting IC components One embodiment provides a system for protecting at least one component in an integrated circuit (IC). The system includes a disconnect element that is electrically connected in series between a terminal of the IC and the at least one component. The disconnect elemen... | 04/15/2008 |
| 7353357 | Apparatus and method for pipelined memory operations A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory ... | 04/01/2008 |
| 7345943 | Unclocked eFUSE circuit An unclocked electrically programmable fuse (eFUSE) system includes at least two resistive voltage dividers, one voltage divider including an eFUSE, and a differential amplifier. An output node of at least one of the voltage dividers includes an eFUSE that changes a... | 03/18/2008 |
| 7339838 | Method and apparatus for supplementary command bus An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured t... | 03/04/2008 |
| 7335957 | Semiconductor memory integrated circuit and layout method of the same A semiconductor memory integrated circuit includes a plurality of pads; a peripheral circuit having a plurality of control circuits which are arranged at locations adjacent to the plurality of the pads and receive a plurality of input signals to generate a plurality... | 02/26/2008 |
| 7336554 | Semiconductor memory device having a reduced number of pins A semiconductor memory device includes an IO circuit for receiving or outputting command signals, address signals and data which are serialized and an IO signal control circuit for parallel converting the serialized command signals, address signals and data inputted... | 02/26/2008 |
| 7333357 | Static random access memory device having reduced leakage current during active mode and a method of operating thereof An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) an arra... | 02/19/2008 |
| 7330951 | Apparatus and method for pipelined memory operations A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and... | 02/12/2008 |
| 7315476 | System and method for communicating information to a memory device using a reconfigured device pin System and method for communicating information to and from memory devices. In one embodiment, the invention includes a memory system having a memory device having at least one extraneous device pin, a memory controller configured to control the memory device and a ... | 01/01/2008 |
