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| Number | Title | Issue Date |
| 8116153 | Read only memory and method of reading same A Read Only Memory (ROM) device includes a ROM array, a row address decoder, a column address decoder, a column multiplexer, and a control circuit. Data is stored in bit cells in the ROM array. The control circuit generates control signals for reading the ROM. The r... | 02/14/2012 |
| 8116149 | Circuit and method for small swing memory signals Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing dif... | 02/14/2012 |
| 8089819 | Semiconductor device and semiconductor signal processing apparatus A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel ... | 01/03/2012 |
| 8072819 | Memory device with parallel interface A memory device including a serial-parallel conversion section that converts serial data into parallel data, a parallel-serial conversion section that converts parallel data into serial data, and a parallel-parallel conversion section that changes a bit width of the... | 12/06/2011 |
| 8072820 | System and method for reducing pin-count of memory devices, and memory device testers for same Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output t... | 12/06/2011 |
| 8036045 | Data output control circuit A data output control circuit in a semiconductor memory device includes a driving signal generating unit configured to decode first and second I/O mode signals and first and second address level signals in response to a bank active signal and generate driving signal... | 10/11/2011 |
| 8031533 | Input circuit of semiconductor memory apparatus and controlling method thereof Disclosed is an input circuit of a semiconductor memory apparatus. The input circuit includes a first buffer and a second buffer. The first buffer has an input terminal connected with a first input pin for receiving a control signal used in a multi-control mode for ... | 10/04/2011 |
| 8023337 | Semiconductor memory device A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding... | 09/20/2011 |
| 8014211 | Keeperless fully complementary static selection circuit Selection circuitry for use in register files, multiplexers, and so forth is disclosed. The selection circuitry includes a plurality of local bit lines coupled to global bit line circuitry. Groups of cells or data inputs are coupled to each of the local bit lines. W... | 09/06/2011 |
| 7995403 | Semiconductor integrated circuit with data bus inversion function A semiconductor integrated circuit includes a data bus inversion (DBI) flag generating unit to generate DBI flag signals using a plurality of output data sets, a data inverting unit to invert the plurality of output data sets according to the DBI flag signals and tr... | 08/09/2011 |
| 7995406 | Data writing apparatus and method for semiconductor integrated circuit A data writing apparatus includes a distributed transmission unit configured to transmit first data and second data, having been aligned to have the same timing, to data lines at mutually different timings, and a data writing unit configured to synchronize the first... | 08/09/2011 |
| 7986583 | Method for designing integrated circuit incorporating memory macro An integrated circuit design method whereby memory instances are assigned to memory macros integrated within an integrated circuit. A plurality of memory instances operating at the same operation frequency are assigned to a single memory macro. A frequency multiplie... | 07/26/2011 |
| 7978553 | Apparatus for controlling I/O strobe signal in semiconductor memory apparatus A sensing enable signal control circuit determines a driving timing of an I/O sense amplifier based on a read-out result of data, which is stored in a dummy cell of a semiconductor memory apparatus. The sensing enable signal control circuit in a semiconductor memory... | 07/12/2011 |
| 7948807 | Semiconductor memory device having a current consumption reduction in a data write path The present invention describes a semiconductor memory device that can reduce current consumption occurring in a data write path. The semiconductor memory device includes a write path over which any one of general data and representative data corresponding to a part... | 05/24/2011 |
| 7940575 | Memory device and method providing logic connections for data transfer In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory c... | 05/10/2011 |
| 7920433 | Method and apparatus for storage device with a logic unit and method for manufacturing same Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory ce... | 04/05/2011 |
| 7881125 | Power reduction in a content addressable memory having programmable interconnect structure A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match lin... | 02/01/2011 |
| 7859914 | Non-volatile memory device, non-volatile memory system and control method for the non-volatile memory device in which driving ability of a selector transistor is varied The control method includes a step of varying driving ability of a selector transistor which selects a diffusion layer in a selected memory cell and a diffusion layer of at least one non-selected memory cell which adjoins to the selected memory cell when the selecte... | 12/28/2010 |
| 7848167 | Apparatus and method for generating wide-range regulated supply voltages for a flash memory A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides... | 12/07/2010 |
| 7826282 | Random access memory for use in an emulation environment A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of s... | 11/02/2010 |
| 7821844 | Content addresable memory having programmable interconnect structure A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match lin... | 10/26/2010 |
| 7813186 | Flash memory device and programming method thereof A flash memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including a plurality of page buffers connected to bit lines of the memory cell array, a data line mux unit connected between the page buffer unit and a data... | 10/12/2010 |
| 7804719 | Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode A programmable logic block provides an improved output delay by bypassing the memory array and multiplexer structure when programmed to function as a random access memory (RAM) and a new value is written to the RAM. A programmable logic block includes memory cells, ... | 09/28/2010 |
| 7791962 | Semiconductor device and semiconductor signal processing apparatus A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel ... | 09/07/2010 |
| 7787275 | Content addressable memory having programmable combinational logic circuits A content addressable memory (CAM) device includes a plurality of independently configurable CAM groups, each CAM group including a number of CAM rows and a programmable combinational logic circuit. Each CAM row includes a plurality of CAM cells coupled to a match l... | 08/31/2010 |
| 7787310 | Circuits, devices, systems, and methods of operation for capturing data signals Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and ca... | 08/31/2010 |
| 7773431 | Systems and methods for reading data from a memory array One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series ... | 08/10/2010 |
| 7768840 | Memory modeling using an intermediate level structural description A computer-implemented method for creating an integrated circuit, IC, test engine for testing a proposed IC memory array using new memory structural model. An IC designer inputs the number of words that can be stored and a column multiplexer ratio in a proposed IC m... | 08/03/2010 |
| 7715250 | Circuitry and method for indicating a memory Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory type... | 05/11/2010 |
| 7710789 | Synchronous address and data multiplexed mode for SRAM A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe s... | 05/04/2010 |
| 7675789 | Programmable heavy-ion sensing device for accelerated DRAM soft error detection Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is... | 03/09/2010 |
| 7663935 | Semiconductor memory device with adjustable I/O bandwidth A semiconductor memory device with adjustable I/O bandwidth includes a plurality of data I/O buffers connected one by one to a plurality of I/O ports, a switch array including a plurality of switches for connecting the plurality of data I/O buffers to a plurality of... | 02/16/2010 |
| 7663936 | Memory circuit and semiconductor device including the memory circuit, the memory circuit including selectors for selecting a data holding circuit A semiconductor circuit of the invention comprises: a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines; a plurality of sense amplifiers each for amplifying data of the memo... | 02/16/2010 |
| 7656716 | Regular expression search engine A system for searching an input string for a number of regular expressions includes a search block and a compiler. The search block includes a plurality of content addressable memory (CAM) devices, wherein each of the CAM devices is differently configured to impleme... | 02/02/2010 |
| 7656715 | Semiconductor memory device A semiconductor memory device includes data transmission devices for transmit data in synchronization with each other. The semiconductor memory device includes a plurality of data transferring unit, a first control unit, a multiplexing unit, and a second control uni... | 02/02/2010 |
| 7643353 | Content addressable memory having programmable interconnect structure A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match lin... | 01/05/2010 |
| 7619935 | Memory device with separate read and write gate voltage controls A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal commu... | 11/17/2009 |
| 7606081 | Device programmable to operate as a multiplexer, demultiplexer, or memory device A device that is programmable to operate as a memory device, a multiplexer, or a demultiplexer includes: a first column decoder; a memory array coupled to the first column decoder; a plurality of selectors coupled to the memory array; and a second column decoder cou... | 10/20/2009 |
| 7590009 | Semiconductor memory apparatus and data masking method of the same A memory apparatus includes: a memory cell block; a data input part that performs signal processing to transmit general data and mask information input to the semiconductor memory apparatus to the memory cell block, and outputs the processed data and information; a ... | 09/15/2009 |
| 7580294 | Semiconductor memory device comprising two rows of pads A semiconductor memory device includes a first row of pads including a first plurality of data input/output (I/O) pads; a second row of pads including a second plurality of data I/O pads; and a first I/O multiplexer associated with the first row of pads and providin... | 08/25/2009 |
