Did You Know...
...that one person who claimed to be the inventor of the television is Russian emigre Vladimir Zworykin? In 1929 David Sarnoff, founder of RCA, asked Zworykin what it would take to develop TV for commercial use. He said: a year and a half and $100,000. In reality, it took 20 years and $50 million! Before his death in 1982 at the age of 92, Zworykin said of his invention: "The technique is wonderful. It is beyond my expectations. But the programs! I would never let my children even come close to this thing."
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| Number | Title | Issue Date |
| 7558123 | Efficient and systematic measurement flow on drain voltage for different trimming in flash silicon characterization Systems and methods that facilitate characterization of a flash memory device are presented. A characterization component can be associated with a regulator component included in a memory device to facilitate setting and measuring respective drain voltage levels for... | 07/07/2009 |
| 7554855 | Hybrid solid-state memory system having volatile and non-volatile memory A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memo... | 06/30/2009 |
| 7489563 | Memory device with adaptive sense unit and method of reading a cell array A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary... | 02/10/2009 |
| 7480188 | Memory Access apparatus A memory access apparatus reading data from a memory, the memory including a terminal that address information is input to, a terminal that a clock signal changing at a predetermined cycle is input to, a terminal that a read command is input to, and a terminal that ... | 01/20/2009 |
| 7468922 | Apparatus and method for dynamically repairing a semiconductor memory An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memo... | 12/23/2008 |
| 7443718 | Magnetic memory device A magnetic memory device comprises a magnetic tunnel junction (MTJ) having a ferromagnetic free layer, and exhibits a first, relatively high resistance state, and a second, relatively low resistance state. To write to the magnetic memory device a current IMTJ | 10/28/2008 |
| 7436715 | Non-volatile memory device, and control method of non-volatile memory device In a memory cell array, aside from a normal-data storing region, a control-information storing region is also allocated, and the control-information storing region is composed of a predetermined number of control-information storing memory cells in each bit of contr... | 10/14/2008 |
| 7437500 | Configurable high-speed memory interface subsystem A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic rando... | 10/14/2008 |
| 7433245 | Memory card able to guarantee a recoding rate and memory card system using the memory card A memory card is equipped in a host apparatus and used for data recording. The memory card has a built-in flash memory and an internal ROM, and there is prestored a predetermined writable block size corresponding to a certain integral multiple of a size of an erase ... | 10/07/2008 |
| 7433793 | Error detection apparatus and method and signal extractor A modulated voltage signal modulated at a predetermined frequency f0 is supplied to an integrated circuit under test to be tested set at an arbitrary stationary point, and an observation signal containing information on power supply current flowing through th... | 10/07/2008 |
| 7433246 | Flash memory device capable of storing multi-bit data and single-big data There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bi... | 10/07/2008 |
| 7417881 | Low power content addressable memory A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled ... | 08/26/2008 |
| 7417914 | Semiconductor memory device A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-... | 08/26/2008 |
| 7414899 | Method and apparatus for early write termination in a semiconductor memory A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a buffer circuit and an early write termination circuit. The buffer ci... | 08/19/2008 |
| 7403416 | Integrated DRAM-NVRAM multi-level memory An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a... | 07/22/2008 |
| 7397708 | Technique to suppress leakage current Embodiments of the invention generally provide a method and wordline driver having a reduced leakage current. In one embodiment, a wordline is driven to a boosted high voltage with a driver transistor of the wordline driver if the wordline driver is in an operationa... | 07/08/2008 |
| 7398554 | Secure lock mechanism based on a lock word One or more lock words in a non-volatile memory with write ability correspond to lockable features of a protected system including the memory. A lockable feature should be locked when the corresponding lock word has a value equal to one of a limited number of predet... | 07/08/2008 |
| 7394704 | Non-volatile semiconductor memory device, electronic card using the same and electronic apparatus A non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circ... | 07/01/2008 |
| 7388791 | Signal interface Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a r... | 06/17/2008 |
| 7388797 | Semiconductor memory device An apparatus for detecting a defect of a data transfer line in a semiconductor memory device, including a data transfer unit for transferring data between a local I/O line and a global I/O line; a data transfer controller for controlling the data transfer unit by ge... | 06/17/2008 |
| 7385844 | Semiconductor device and method of controlling the same A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the ... | 06/10/2008 |
| 7385838 | Semiconductor device with a non-erasable memory and/or a nonvolatile memory A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the per... | 06/10/2008 |
| RE40356 | Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells locate... | 06/03/2008 |
| 7379324 | Storage device The present invention provides a storage device including a first electrode, a plurality of second electrodes arranged opposite the first electrode across a gap, and a particle which is selectively placed in one of the gaps between the first electrode and the second... | 05/27/2008 |
| 7379363 | Method and apparatus for implementing high speed memory Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be... | 05/27/2008 |
| 7379347 | Memory device and method for performing write operations in such a memory device A memory device and method of performing a write operation in such a memory device are provided. The memory device comprises a memory array having a plurality of memory cells, and a plurality of word lines and a plurality of bit lines via which the plurality of memo... | 05/27/2008 |
| 7376020 | Memory using a single-node data, address and control bus An integrated circuit digital device is coupled to a memory with a single-node data, address and control bus. The memory may be a non-volatile memory and/or volatile memory. The memory may be packaged in a low pin count integrated circuit package. The memory integra... | 05/20/2008 |
| 7376889 | Memory device capable of detecting its failure A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data inp... | 05/20/2008 |
| 7376021 | Data output circuit and method in DDR synchronous semiconductor device Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted ... | 05/20/2008 |
| 7372725 | Integrated circuit having resistive memory A memory device including a memory cell, a first circuit, and a second circuit. The memory cell includes phase-change material. The first circuit is configured to provide pulses to the phase-change material and to program each of more than two states into the memory... | 05/13/2008 |
| 7372730 | Method of reading NAND memory to compensate for coupling between storage elements A method for reading a non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The method includes the steps of: selecting a bit to be read in a word-line; reading an adjacent word line writte... | 05/13/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7372745 | Semiconductor memory device with no latch error A dynamic random access memory (DRAM) includes a data signal input circuit configured to input a data signal in response to a data control signal, and a data strobe signal input circuit configured to input a data strobe signal in response to a data strobe control si... | 05/13/2008 |
| 7372717 | Methods for resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage su... | 05/13/2008 |
| 7372763 | Memory with spatially encoded data storage In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The first delay element is controlled by data bits that are to be written ... | 05/13/2008 |
| 7369443 | Semiconductor device with adjustable signal drive power A semiconductor device includes a terminal configured to receive a first signal that is set from an exterior at a time of operation, a memory unit configured to retain a state of a setting fixedly regardless of whether at the time of operation or at a time of no ope... | 05/06/2008 |
| 7369444 | Early read after write operation memory device, system and method A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write da... | 05/06/2008 |
| 7369446 | Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high ser... | 05/06/2008 |
| 7370140 | Enhanced DRAM with embedded registers An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these regis... | 05/06/2008 |
| 7370166 | Secure portable storage device In one embodiment of the present invention, a secure storage system includes a removable storage device having a secure storage area for storage of secure data and a public storage area and device port for coupling the removable storage device to a host, the removab... | 05/06/2008 |
