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| Number | Title | Issue Date |
| 7437252 | Configurable voltage regulator A voltage regulator having a device characteristic comprises a first terminal connectable to a first external impedance. A measurement circuit communicates with the first terminal to measure the first external impedance. A control circuit controls the device charact... | 10/14/2008 |
| 7310266 | Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing inform... | 12/18/2007 |
| 7271440 | Method and apparatus for forming an integrated circuit electrode having a reduced contact area A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A re... | 09/18/2007 |
| 7242610 | Ultraviolet erasable semiconductor memory device Each memory cell of an EPROM contains two MOSFETs and a data of each memory cell is read out by detecting a current difference between the two MOSFETs by using a differential amplifier. In such constitution as described above, even when the data is erased by irradia... | 07/10/2007 |
| 7135756 | Array of cells including a selection bipolar transistor and fabrication method thereof A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collec... | 11/14/2006 |
| 7106642 | Semiconductor integrated circuit device in which a measure to counter soft errors is taken A semiconductor integrated circuit device includes a first memory circuit which stores normal data, a second memory circuit which stores determination information used to determine whether a value of the normal data is changed or not, and a determination circuit whi... | 09/12/2006 |
| 7084451 | Circuits with a trench capacitor having micro-roughened semiconductor surfaces A method for forming a trench capacitor. The method includes forming a trench in a semiconductor substrate. A conformal layer of semiconductor material is deposited in the trench. The surface of the conformal layer of semiconductor material is roughened. An insulato... | 08/01/2006 |
| 7082048 | Low voltage operation DRAM control circuits Circuits and methods are described for reducing leakage current and speeding access within dynamic random access memory circuit devices. A number of beneficial aspects are described. A circuit is described for an enhanced sense amplifier utilizing complementary drai... | 07/25/2006 |
| 7075834 | Semiconductor integrated circuit device A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mo... | 07/11/2006 |
| 7072205 | Floating-body DRAM with two-phase write A row of floating-body single transistor memory cells is written to in two phases. ... | 07/04/2006 |
| 7057223 | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are... | 06/06/2006 |
| 7049196 | Vertical gain cell and array for a dynamic random access memory and method for forming the same A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical pillar of semiconductor material is provided. The body portion of the... | 05/23/2006 |
| 6857099 | Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the ... | 02/15/2005 |
| 6849947 | Semiconductor device and pattern layout method thereof The semiconductor device of the invention includes transistors for a driver and dummy patterns formed to be adjacent to the end portion of each output bit group constituting a cathode driver, anode drivers and anode drivers. ... | 02/01/2005 |
| 6742169 | Semiconductor device In the driver for driving display having an anode driver, a cathode driver, and memory portions of a semiconductor device of the invention, anode driver regions connected to the memory portions are laid out equally in the chip, and SRAMs and are arranged equally in ... | 05/25/2004 |
| 6586787 | Single electron device A single electron device. Fabricated from nanoparticle derivatives, particularly from Au and fullerene nanoparticle derivatives, the device reduces thermal fluctuation in the nanoparticle array and has 15 nm of spacing between two electrodes.... | 07/01/2003 |
| 6587367 | Dummy cell structure for 1T1C FeRAM cell array A ferroelectric memory structure is described for the 1T1C arrangement in ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplif... | 07/01/2003 |
| 6487112 | Single-electron memory A memory device in which each cell includes two portions of isolated-granular material: one portion forms the channel of a single-electron transistor, and the other provides a hysteretic I-V relationship in the gate circuit of the transistor.... | 11/26/2002 |
| 5742086 | Hexagonal DRAM array Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by o... | 04/21/1998 |
| 5732037 | Semiconductor memory A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of... | 03/24/1998 |
| 5689457 | Semiconductor Memory A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of... | 11/18/1997 |
| 5640350 | Multi-bit dynamic random access memory cell storage A single transistor capacitor stacked memory cell utilizing precharge voltage and spacial format to miximize storage per unit of area.... | 06/17/1997 |
| 5473178 | Semiconductor memory cell for holding data with small power consumption A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage nod... | 12/05/1995 |
| 5241507 | One transistor cell flash memory assay with over-erase protection A memory array formed from single transistor flash cells employs prevention circuitry for minimizing the effect of any floating gates in an over-erased state when accessing data stored in the memory array device. The prevention circuit includes a column l... | 08/31/1993 |
| 5222040 | Single transistor EEPROM memory cell A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area wherein a tunneling of charge can take place between the drain and the... | 06/22/1993 |
| 5218569 | Electrically alterable non-volatile memory with n-bits per memory cell The bit storage density of an Electrically Alterable Non-Volatile Memory (EANVM) cell is improved by increasing the number of bits that are stored on an individual memory cell, without increasing the size and complexity of the memory cell, by allowing a n... | 06/08/1993 |
| 5170374 | Semiconductor memory A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of... | 12/08/1992 |
| 5119332 | Semiconductor memory A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of... | 06/02/1992 |
| 5029130 | Single transistor non-valatile electrically alterable semiconductor memory device A single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is over the source, channel and drain reg... | 07/02/1991 |
| 4979149 | Non-volatile memory device including a micro-mechanical storage element A memory device for digital electronic signals includes at least one micro-mechanical memory element. The memory element includes a support having recess defined therein and a curved mechanical component bridging the recess and fixed to the support. The m... | 12/18/1990 |
| 4961095 | Semiconductor memory device with word lines adjacent and non-intersecting with capacitor grooves A grooved separating region 112 having information electric charge storing capacitances CP formed on side surfaces thereof is formed to extend the region between the adjacent word line 107 in parallel with the word line 107. As a result, the gr... | 10/02/1990 |
| 4860255 | Semiconductor memory A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of... | 08/22/1989 |
| 4771323 | Semiconductor memory device In a semiconductor memory device, a memory cell comprises a first MOS transistor (Q1) of a first channel type formed on a semiconductor substrate and having a gate electrode connected to a word line. A charge storage electrode is connected to the drain of... | 09/13/1988 |
| 4758986 | Single transistor cell for electrically-erasable programmable read-only memory and array thereof A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing ... | 07/19/1988 |
| 4746959 | One-transistor memory cell for large scale integration dynamic semiconductor memories and the method of manufacture thereof A one-transistor memory cell comprises a semiconductor body which has a thin insulating layer on a boundary surface and a conductive layer on the thin insulating layer, the conductive layer representing that electrode of a storage capacitor that is connec... | 05/24/1988 |
| 4709353 | Semiconductor memory A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of... | 11/24/1987 |
| 4641279 | Semiconductor memory device having a dummy cell and a memory cell which is twice the size of the dummy cell In a semiconductor memory device including memory and dummy cells connected to groups of data lines, word lines and dummy word lines for selecting the memory and dummy cells, respectively, and a signal detector for differentially amplifying the read signa... | 02/03/1987 |
| 4638460 | Semiconductor memory device A semiconductor memory device is provided with memory cells which each comprises an insulated gate type field effect transistor and a capacitor connected in series with one another and connected to bit lines. The capacitor is composed of a pair of electro... | 01/20/1987 |
| 4622570 | Semiconductor memory A semiconductor memory device of a one-transistor type is manufactured by using a so-called double-layer technology. The device comprises a buried-channel type transistor having normally-off characteristics and a capacitor having normally-on characteristi... | 11/11/1986 |
| 4612565 | Semiconductor memory device In a dynamic memory having a plurality of memory cells each of which consists of a MIS type field effect transistor and a charge storing capacitor connected thereto; a dynamic memory is disclosed wherein one electrode of the capacitor is made of a semicon... | 09/16/1986 |
