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| Number | Title | Issue Date |
| 7885123 | Integrated circuit for memory card and memory card using the circuit An integrated circuit for storing data, and for application in a memory card that operates in cooperation with at least one of an external acquisition system and an external processing system includes input/output terminals for receiving the data to be stored, and a... | 02/08/2011 |
| 7821841 | Method of detecting a light attack against a memory device and memory device employing a method of detecting a light attack A memory device having a plurality of memory cells employs a method to detect a light attack on the memory device. The method utilizes at least one memory cell to detect a light attack when the memory cell is in an inactive state, and outputs a signal indicating whe... | 10/26/2010 |
| 7342834 | Data storage having injected hot carriers and erasable when selectively exposed to ambient light radiation A data storage includes a part of functioning for, when data reading operation is carried out on a storage part storing data for a case where the data storage is handled in a predetermined manner, causing predetermined data different from target data to be read out ... | 03/11/2008 |
| 7247357 | Image display device The image display device has a display section formed of plural pixels and a control section which controls the display section, and is provided with nonvolatile phase-change type pixel memories in respective ones of the pixels, or is provided with a nonvolatile pha... | 07/24/2007 |
| 7218555 | Imaging cell that has a long integration period and method of operating the imaging cell The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated e... | 05/15/2007 |
| 7199663 | Use of analog-valued floating-gate transistors for parallel and serial signal processing Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circu... | 04/03/2007 |
| 7102438 | Autozeroing floating-gate amplifier An autozeroing floating-gate amplifier (AFGA) is implemented utilizing a programmable gain element, the characteristics of which may be changed by changing the amount of charge stored on a floating gate device. ... | 09/05/2006 |
| 7087182 | Process of forming an electrically erasable programmable read only memory with an oxide layer exposed to hydrogen and nitrogen The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thu... | 08/08/2006 |
| 7061324 | Use of analog-valued floating-gate transistors for parallel and serial signal processing Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circu... | 06/13/2006 |
| 7049872 | Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined circuits Methods of and apparatuses for matching the signal delay, clock timing, frequency response, gain, offset, and/or transfer function of signal pathways in electrical circuits such as, for example, time-interleaved and pipelined circuits using analog-valued floating-ga... | 05/23/2006 |
| 7038270 | Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same A non-volatile memory device with a non-planar gate insulating layer and a method of fabricating the same are provided. The device includes a tunnel insulating pattern, a charge storage layer, an upper insulating layer and a control gate electrode which are sequenti... | 05/02/2006 |
| 7038544 | Use of analog-valued floating-gate transistors for parallel and serial signal processing Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circu... | 05/02/2006 |
| 7027348 | Power efficient read circuit for a serial output memory device and method An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in ... | 04/11/2006 |
| 6969654 | Flash NVROM devices with UV charge immunity A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions ... | 11/29/2005 |
| 6970386 | Method and apparatus for detecting exposure of a semiconductor circuit to ultra-violet light A method and apparatus are disclosed for detecting if a semiconductor circuit has been exposed to ultra-violet light. An ultra-violet light detection circuit detects exposure to ultra-violet light and will automatically activate a security violation signal. The secu... | 11/29/2005 |
| 6909162 | Surface passivation to reduce dark current in a CMOS image sensor A method for reducing dark current in a photodiode is disclosed. The photodiode comprises a N-well formed in a P-substrate. The method comprises doping the surface of said N-well with a nitrogen dopant. Alternatively, an oxygen or silicon dopant may be used. Still a... | 06/21/2005 |
| 6882574 | Single poly UV-erasable programmable read only memory An erasable programmable read only memory includes two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein a first P-type MOS transistor acts as select transistor, a gate of the first P-type MOS transistor is coupled to select gate voltage... | 04/19/2005 |
| 6580630 | Initialization method of P-type silicon nitride read only memory The presents invention provides an initialization method of a P-type silicon nitride read only memory. A P-type silicon nitride read only memory is provided. An ultra-violet light is uniformly radiated onto the P-type silicon nitride read only memory. Ele... | 06/17/2003 |
| 6437398 | One-time UV-programmable non-volatile semiconductor memory and method of programming such a semiconductor memory One-time UV-programmable read-only memory (1) comprising a number of memory cells in the form of MOS transistors (T) which are arranged in a matrix of rows and columns, each transistor comprising a source and a drain zone (12) and a channel zone (13) form... | 08/20/2002 |
| 6313502 | Semiconductor device comprising a non-volatile memory which is erasable by means of UV irradiation The invention proposes a simple method to lower the threshold voltage of UV erased EPROM and OTP memories. During the erasure, a voltage is applied to the control gate (10) or wordline (2) which is on-chip generated as a photovoltage by means of photodiod... | 11/06/2001 |
| 6249456 | Secured EEPROM memory comprising means for the detection of erasure by ultraviolet radiation A secured electrically modifiable non-volatile memory includes a circuit to determine if memory cells therein have been exposed to ultraviolet radiation. The memory includes at least one additional memory cell, called a reference cell, and an associated r... | 06/19/2001 |
| 6178119 | Method of erasing a non-volatile memory To improve the efficiency of UV erasing in a non-volatile memory, there is proposed to carry out the erase step at an elevated temperature, for example, a temperature lying between 200 and 300° C. In this way a decrease of about 0.5 volt of the threshold... | 01/23/2001 |
| 6034889 | Electrically erasable and programmable non-volatile memory having a protectable zone and an electronic system including the memory An electrically erasable and programmable non-volatile semiconductor memory includes memory registers that are addressable individually or by blocks. The memory also has a protection register in which a protection word can be written. The protection word ... | 03/07/2000 |
| 5969993 | Method of restoring data in non-volatile semiconductor memory Disclosed is a method of restoring data in a non-volatile semiconductor memory which has a memory cell array that a plurality of electrically programmable memory cells to be set of several threshold voltages are matrix-disposed, a data erasing means that ... | 10/19/1999 |
| 5656521 | Method of erasing UPROM transistors The failure rate of semiconductor devices containing UPROM transistors is improved by erasing the UPROM transistors using X-rays. The semiconductor devices are subsequently exposed to UV radiation to erase other transistors charged during X-ray exposure.... | 08/12/1997 |
| 5654921 | Non-volatile memory device equipped with means to electrically erase data The non-volatile memory includes a word line potential control circuit in a non-volatile memory having a memory cell array, word lines, bit lines, an X decoder, a bit line selector, and a source voltage applying circuit. The word line potential control ci... | 08/05/1997 |
| 5592416 | Electronic storage circuit An electronic storage circuit for storing information, in particular switch control information for alternately switching circuit parts of integrated monolithic circuits, having two series connections inserted between the two poles of a voltage supply sou... | 01/07/1997 |
| 5541878 | Writable analog reference voltage storage device A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Circuitry is provided so that all floating gate storage devices can be programmed to their target voltages individually or in paral... | 07/30/1996 |
| 5455785 | Many time programmable memory card with ultraviolet erasable memory A memory card includes a circuit board bearing UV-erasable memory circuits enclosed in an opaque cover. The cover is provided with openings over the memory circuits. These openings can be covered or uncovered by a removable, opaque window shield. The memo... | 10/03/1995 |
| 5386388 | Single cell reference scheme for flash memory sensing and program state verification A reference scheme for verifying the erasing and programming in an electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate which employs a plurality of memory cells, each of which contains a floating gate. Th... | 01/31/1995 |
| 5343434 | Nonvolatile semiconductor memory device and manufacturing method and testing method thereof In a memory device in a bare chip state which is determined as fail by over erasing during a test at a wafer level, information indicating the presence of an over-erased memory cell is stored in a nonvolatile and readable manner into an identification mem... | 08/30/1994 |
| 5270969 | Electrically programmable nonvolatile semiconductor memory device with nand cell structure The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuits. In the data... | 12/14/1993 |
| 5262987 | Floating gate semiconductor nonvolatile memory having impurity doped regions for low voltage operation A semiconductor nonvolatile memory has a base semiconductor region of one conductivity type. A first semiconductor region of the one conductivity type is formed in a surface portion of the base semiconductor region and has an impurity density higher than ... | 11/16/1993 |
| 5255219 | Ultraviolet-erasable type nonvolatile semiconductor memory device having asymmetrical field oxide structure For obtaining improved writing characteristics, a reduced source resistance and an increased cell current of a ultraviolet-erasable type nonvolatile semiconductor memory device, a plurality of field oxide films with an asymmetrical pattern are provided wh... | 10/19/1993 |
| 5243559 | Semiconductor memory device A semiconductor memory device including a semiconductor substrate of a first conduction type, a memory cell having a floating gate and a control gate which are formed on a main surface of the semiconductor substrate and stacked with an interlayer insulati... | 09/07/1993 |
| 5235541 | Integrated circuit entirely protected against ultraviolet rays An integrated circuit ultraviolet-unerasable floating-gate memory, which includes EEPROM (or EPROM) memory cells totally enclosed by a metal mask. The metal mask includes metal projections which are anchored in substrate diffusions, to define a ring compl... | 08/10/1993 |
| 5229972 | Nonvolatile semiconductor memory system An EPROM integrated circuit includes a plurality of banks. When a data write operation is to be performed for this EEPROM integrated circuit, a bank which is used once is not used again, but the operation is constantly performed for new banks. In order to... | 07/20/1993 |
| 5198998 | Erasable programmable read only memory A read only semiconductor memory includes a memory cell matrix including a number of floating-gate type erasable programmable memory cells. A column selector being connected between a plurality of column lines of the memory cell matrix and a writing circu... | 03/30/1993 |
| 5197029 | Common-line connection for integrated memory array A common connection to reduces the amount of chip area required to perform read and programming functions, particularly where signals such as read, programming, supply voltage and data signals are generated from remote locations on the memory chip. The co... | 03/23/1993 |
| 5191551 | Non-volatile semiconductor memory device with transistor paralleling floating gate transistor A non-volatile semiconductor memory device is formed by a plurality of memory cell array groups arranged in a matrix form. Each of the memory cell array groups includes a transistor group. The transistor group is composed of a plurality of transistor pair... | 03/02/1993 |
