Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8164959 | Method and system for programming non-volatile memory cells based on programming of proximate memory cells A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the pr... | 04/24/2012 |
| 8081520 | Over erase correction method of flash memory apparatus An over erase correction method of a flash memory apparatus is provided. The flash memory apparatus includes at least a microprocessor, a memory array, a bit line exchange unit and a column decoder. By controlling the column decoder of the flash memory during a peri... | 12/20/2011 |
| 7929353 | Method and apparatus for adaptive memory cell overerase compensation A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device (100) is provided for performing the adaptively compensating erase verify operation (500, 600). The memory device (100) includes a... | 04/19/2011 |
| 7746706 | Methods and systems for memory devices One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the re... | 06/29/2010 |
| 7746707 | Nonvolatile semiconductor memory device A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, ... | 06/29/2010 |
| 7701780 | Non-volatile memory cell healing Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gat... | 04/20/2010 |
| 7630256 | Erase operation in a flash drive memory A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verif... | 12/08/2009 |
| 7623390 | Programming method for non-volatile memory and non-volatile memory-based programmable logic device A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment inc... | 11/24/2009 |
| 7619934 | Method and apparatus for adaptive memory cell overerase compensation A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device (100) is provided for performing the adaptively compensating erase verify operation (500, 600). The memory device (100) includes a... | 11/17/2009 |
| 7599229 | Methods and structures for expanding a memory operation window and reducing a second bit effect Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first me... | 10/06/2009 |
| 7599228 | Flash memory device having increased over-erase correction efficiency and robustness against device variations A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source reg... | 10/06/2009 |
| 7499338 | Partitioned soft programming in non-volatile memory Soft programming is performed to narrow the threshold voltage distribution of a set of erased memory cells. Soft programming can shift the threshold voltage of memory cells closer to a verify level for the erased state. A set of memory cells can be soft programmed b... | 03/03/2009 |
| 7483311 | Erase operation in a flash memory device A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verif... | 01/27/2009 |
| 7460412 | Flash memory device and erasing method thereof A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address for selecting the next word line, whether the incremented address matc... | 12/02/2008 |
| 7457167 | Method for preventing over-erasing of unused column redundant memory cells in a flash memory having single-transistor memory cells A method is provided for testing and for preventing over-erasure of unused redundant memory cells that can be subsequently used to replace defective memory cells in a Flash memory. An unused redundant memory cell is preprogrammed and tested simultaneously with each ... | 11/25/2008 |
| 7443732 | High performance flash memory device capable of high density data storage A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programmin... | 10/28/2008 |
| 7420853 | Semiconductor storage device and semiconductor storage device driving method A semiconductor storage device comprises a semiconductor layer; a plurality of memory cells formed on the semiconductor layer, data writing, erasing or reading with respect to each of the memory cells being possible based on a voltage applied to a control electrode ... | 09/02/2008 |
| 7415646 | PageEXE erase algorithm for flash memory Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase algorithm to verify and repeatedly erase the sector until a portion of th... | 08/19/2008 |
| 7400537 | Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can in... | 07/15/2008 |
| 7391655 | Data processing system and nonvolatile memory Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls a... | 06/24/2008 |
| 7372733 | Non-volatile semiconductor memory device having different erase pass voltages for respective memory sectors and associated erase method A non-volatile semiconductor memory device comprises a plurality of memory sectors arranged in different memory banks having different bulk regions. The memory cells can be erased using a first mode erase operation, which determines different erase pass voltages for... | 05/13/2008 |
| 7366020 | Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string ... | 04/29/2008 |
| 7362610 | Programming method for non-volatile memory and non-volatile memory-based programmable logic device A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment inc... | 04/22/2008 |
| 7355893 | Semiconductor memory device and method for writing to semiconductor memory device The semiconductor memory device comprising: an n-channel memory cell transistor including: a first diffused region and a second diffused region formed in a semiconductor substrate; a charge storage layer formed over the semiconductor substrate between the first diff... | 04/08/2008 |
| 7355897 | Methods to resolve hard-to-erase condition in charge trapping non-volatile memory A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a ... | 04/08/2008 |
| 7355894 | Programming flash memories A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control circuit for controlling access to the array of flash memory cells. The command control circuit is adapted... | 04/08/2008 |
| 7353325 | Wear leveling techniques for flash EEPROM systems A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by ... | 04/01/2008 |
| 7348247 | Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing the same are disclosed. A disclosed semiconductor device comprises a semiconductor substrate; a gate formed on the semiconductor substrate; a gate oxide layer interposed between the semiconductor substrate and the g... | 03/25/2008 |
| 7345922 | Position based erase verification levels in a flash memory device The location of a cell to be erase verified is determined. The erase verification threshold voltage is then set. The threshold voltage is changed in response to the cell's location with respect to array ground. A cell in the middle of a row of cells between array gr... | 03/18/2008 |
| 7339822 | Current-limited latch A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A curre... | 03/04/2008 |
| 7336536 | Handling defective memory blocks of NAND memory devices Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively preventing testing of the respective memory block coupled thereto when that ... | 02/26/2008 |
| 7323744 | Semiconductor device and fabrication method therefor A semiconductor device includes an ONO film (17) formed on a semiconductor substrate (15), a first gate (14), the first gate (14) formed on the ONO film (17), a source (10) and a drain (12) provided at both sides of t... | 01/29/2008 |
| 7324385 | Molecular memory Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufact... | 01/29/2008 |
| 7321511 | Semiconductor device and method for controlling operation thereof A semiconductor device includes a semiconductor substrate, word lines, global bit lines, and inversion gates that form inversion layers serving as local bit lines in the semiconductor substrate. The inversion layers are electrically connected to the global bit lines... | 01/22/2008 |
| 7319614 | Non-volatile semiconductor memory device and data programming method In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispers... | 01/15/2008 |
| 7319630 | Current-limited latch A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A curre... | 01/15/2008 |
| 7319615 | Ramp gate erase for dual bit flash memory A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater ... | 01/15/2008 |
| 7305513 | Circuit for preventing nonvolatile memory from over-erase A method for preventing the over-erase in a nonvolatile memory comprises the following steps. First, at least one normal cell of the nonvolatile memory and at least one reference cell that corresponds to the at least one normal cell are provided with a constant curr... | 12/04/2007 |
| 7304890 | Double byte select high voltage line for EEPROM memory block A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the ... | 12/04/2007 |
| 7301820 | Non-volatile memory dynamic operations A dynamic programming method for a non-volatile storage device is described. Memory cells are provided arrayed in R rows. Sub bit lines are provided coupled to voltage supply lines through select circuits. During program operation, the select circuits are switched s... | 11/27/2007 |
