Quotables
"The radio craze will die out in time."
Thomas Edison ; 1922
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8189397 | Retention in NVM with top or bottom injection Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providi... | 05/29/2012 |
| 8189398 | Read operation method of memory device A read operation method of a memory device includes applying a first voltage to each of a first memory cell and a second memory cell during a first read operation, applying the first voltage to the first memory cell and a second voltage to the second memory cell dur... | 05/29/2012 |
| 8174904 | Memory array and method of operating one of a plurality of memory cells An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of t... | 05/08/2012 |
| 8174903 | Method of operating nonvolatile memory device A method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes prechargi... | 05/08/2012 |
| 8174902 | Flash memory and a method for programming the flash memory in which a bit line setup operation is executed simultaneously with a channel pre-charge operation A method, device and system are provided for programming a flash memory device, the method including executing a bit line setup operation, and executing a channel pre-charge operation simultaneously with the bit line setup operation, the channel pre-charge operation... | 05/08/2012 |
| 8144521 | Method of operating nonvolatile memory device A method of operating a nonvolatile memory device comprising cell strings each comprising memory cells coupled in series between a drain select transistor and a source select transistor, including precharging a sense node to thereby precharge a bit line coupled to t... | 03/27/2012 |
| 8120969 | Semi-volatile NAND flash memory Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash memory may be partitioned into various retention regions. Other embodiments may be described and claimed.... | 02/21/2012 |
| 8102717 | Method of testing for a leakage current between bit lines of nonvolatile memory device A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, suppl... | 01/24/2012 |
| 8098528 | Voltage generation circuit and nonvolatile memory device including the same A high voltage generation circuit includes a clock logic unit configured to generate a switch clock signal and a pump clock signal, that has a varying frequency, in response to an input signal, a high voltage unit configured to generate a high voltage in response to... | 01/17/2012 |
| 8089814 | Method of reading data in a non-volatile memory device A method of reading data in a non-volatile memory device compensates for a change in a reading/verifying result in accordance with a change of temperature. The method includes sensing a temperature of memory cells, setting a first voltage and a second voltage of a b... | 01/03/2012 |
| 8085600 | Program and verify method of nonvolatile memory device A program and verify method of a nonvolatile memory device, which can minimize the time taken for program and verify operations. The program and verify method includes precharging an output terminal of a block selector to a second level, making the output terminal o... | 12/27/2011 |
| 8085601 | Programming method and initial charging method of nonvolatile memory device A programming method of a nonvolatile memory device includes precharging bit lines of the nonvolatile memory device based on loaded data, boosting channels corresponding to the respective precharged bit lines, after supplying word lines adjacent to a selected word l... | 12/27/2011 |
| 8059472 | Process and temperature tolerant non-volatile memory A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends o... | 11/15/2011 |
| 8059471 | Method and apparatus of operating a non-volatile DRAM A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-ga... | 11/15/2011 |
| 8054692 | Flash memory device reducing noise of common source line, program verify method thereof, and memory system including the same A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to st... | 11/08/2011 |
| 8054693 | Capacitorless dynamic memory device capable of performing data read/restoration and method for operating the same In example embodiments, the semiconductor memory device, and the method for operating the semiconductor memory device, includes a memory cell array having a plurality of memory cells each formed of a transistor having a floating body. The transistors are coupled bet... | 11/08/2011 |
| 8050104 | Non-volatile memory device and system having reduced bit line bias time A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and configured to precharge the bit lines, a page buffer precharging the plural... | 11/01/2011 |
| 8045396 | Memory and reading method thereof A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit lin... | 10/25/2011 |
| 8040738 | Method and apparatus for performing semiconductor memory operations A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller pro... | 10/18/2011 |
| 8031530 | Method of performing read operation of nonvolatile memory device In a method of performing a read operation of a nonvolatile memory device, a selected bit line is precharged. A pass voltage is sequentially applied to all word lines. The pass voltage applied to a word line, selected from among all the word lines, is changed for a ... | 10/04/2011 |
| 8031531 | Incremental memory refresh A memory system comprises charge storage cells and a refresh control module. The charge storage cells have a charge level decay that is based on lifetime erase operations performed on the charge storage cells. The refresh control module increases charge levels of th... | 10/04/2011 |
| 8023335 | Flash memory device and systems and reading methods thereof A read method of a flash memory device is provided which comprises reading a plurality of adjacent memory cells connected with a word line different from a plurality of selected memory cells; reading the plurality of selected memory cells one or more times using a p... | 09/20/2011 |
| 8018779 | Semiconductor storage device It has been conventionally difficult to make circuits operate faster. The present invention is a semiconductor storage device including a reference voltage circuit that supplies a reference voltage, and first and second memory circuits, that performs a read/write op... | 09/13/2011 |
| 8004904 | Semiconductor integrated circuit device A semiconductor integrated circuit device capable of shortening a chip reset period (time) is provided. The semiconductor integrated circuit device has a nonvolatile memory which performs a reading operation of trimming information after completion of precharge of a... | 08/23/2011 |
| 8000152 | Charge pump operation in a non-volatile memory device A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from ... | 08/16/2011 |
| 8000151 | Semiconductor memory column decoder device and method Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data r... | 08/16/2011 |
| 7995399 | NAND memory device and programming methods A NAND Flash memory device reduces circuitry noise during program operations. The memory includes bit lines that are electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation on the bit lines. A NAND ... | 08/09/2011 |
| 7986562 | Controlling AC disturbance while programming A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during... | 07/26/2011 |
| 7983091 | Divided bitline flash memory array with local sense and signal transmission A flash memory array and a method for performing read operation therein are disclosed. The flash memory array comprises a plurality of memory segment, a data cache and a plurality of data handlers coupled between a pair of memory segment and between a memory segment... | 07/19/2011 |
| 7961523 | Nonvolatile memory device and programming method Disclosed is a programming method for a nonvolatile memory device. The method includes; charging word-line signal lines to a pass voltage during a pass voltage charge operation, simultaneously executing an initial precharge operation for strings including program-in... | 06/14/2011 |
| 7957200 | Semiconductor memory device and read access method thereof The semiconductor memory device includes a plurality of memory cell arrays and a control circuit that outputs a first signal and a second signal. The first signal instructs start of precharging of each memory cell array. The second signal instructs completion of the... | 06/07/2011 |
| 7957201 | Flash memory device operating at multiple speeds A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The ... | 06/07/2011 |
| 7948806 | Device with precharge/homogenize circuit A device with a precharge/homogenize circuit. One embodiment provides at least one switching element is acting as a homogenizer, and at least one switching element is acting as a precharger. The diffusion region of the switching element acting as a homogenizer is se... | 05/24/2011 |
| 7936610 | Selective refresh of single bit memory cells Methods and systems to selectively refresh a single bit per cell non-volatile memory cell to reduce memory cell errors. In an embodiment, a memory device scans its memory cells, performing a multi-level read on memory cells in a single bit per cell mode. Depending o... | 05/03/2011 |
| 7936618 | Memory circuit and method of sensing a memory element The memory circuit comprises at least one memory element (T1), a sense amplifier (SA) for sensing a state of the memory element (T1), a switching device (T2) for selectively coupling the sense amplifier (SA) to the memory element (T1), Th... | 05/03/2011 |
| 7924627 | Semiconductor memory device In a semiconductor memory device, a voltage rise due to IR-DROP is suppressed which occurs when a ground voltage is applied to a memory cell during a program operation. Discharge transistors are provided between the ground and bit lines connected to the source and d... | 04/12/2011 |
| 7903471 | Method for improving memory device cycling endurance by providing additional pulses A method for programming and erasing a PHINES memory device is comprising providing one or more additional pulses that are associated with a program or erase pulse, wherein the additional pulses are of similar polarity, but of lesser magnitude than the program or er... | 03/08/2011 |
| 7903469 | Nonvolatile semiconductor memory, its read method and a memory card A nonvolatile semiconductor memory includes a memory cell array having a plurality of NAND cell units which are arranged with a plurality of memory cells connected in series and a first selection transistor and a second selection transistor which are each connected ... | 03/08/2011 |
| 7903470 | Integrated circuits and discharge circuits An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a firs... | 03/08/2011 |
| 7898872 | Operating method used in read or verification method of nonvolatile memory device In an operating method in a read or verification operation of a nonvolatile memory device, selected bit lines are precharged to a logic high level and, at the same time, unselected bit lines are discharged to a logic low level. The selected and unselected bit lines ... | 03/01/2011 |
