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| Number | Title | Issue Date |
| 8179727 | NAND flash memory devices and methods of LSB/MSB programming the same Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the ma... | 05/15/2012 |
| 8169833 | Partitioning process to improve memory cell retention Subject matter disclosed herein relates to improving memory cell retention for non-volatile flash memory. ... | 05/01/2012 |
| 8154930 | Semiconductor memory device which stores plural data in a cell A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circ... | 04/10/2012 |
| 8149628 | Operating method of non-volatile memory device A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the... | 04/03/2012 |
| 8130553 | Systems and methods for low wear operation of solid state memory This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data ... | 03/06/2012 |
| 8125833 | Adaptive dynamic reading of flash memories A data storage device includes a controller and storage elements. The controller is configured to read a threshold voltage of each of a plurality of the storage elements to generate read threshold data and to assign reference voltages defining each of a plurality of... | 02/28/2012 |
| 8116141 | Method analyzing threshold voltage distribution in nonvolatile memory A distribution analyzing method for a nonvolatile memory device having memory cells exhibiting overlapping first and second threshold voltage distributions includes; detecting a degree of overlap between the first and second threshold voltage distributions by readin... | 02/14/2012 |
| 8085599 | Memory device and method for estimating characteristics of multi-bit programming Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states select... | 12/27/2011 |
| 8081518 | Semiconductor memory device A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected... | 12/20/2011 |
| 8077524 | Correcting for over programming non-volatile storage A non-volatile storage system corrects over programed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line). ... | 12/13/2011 |
| 8064266 | Memory devices and methods of writing data to memory devices utilizing analog voltage levels Memory devices, and methods of writing data to memory devices, utilizing analog voltage levels indicative of threshold voltages and desired threshold voltages of memory cells. ... | 11/22/2011 |
| 8050103 | Method of programming nonvolatile memory device In one aspect of the method of programming a nonvolatile memory device, memory cells selected for a program are determined to belong to a first memory cell group or a second memory cell group based on address information and a program command. According to this dete... | 11/01/2011 |
| 8040737 | Gain control for read operations in flash memory A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M-1 read thre... | 10/18/2011 |
| 8031529 | Memory cell threshold voltage drift estimation methods and apparatus Methods of operating memory devices include determining a threshold voltage drift of two or more reference memory cells of the memory device programmed to only a subset of data states of the memory device and, using the determined threshold voltage drift of the two ... | 10/04/2011 |
| 8023334 | Program window adjust for memory cell signal line delay A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propag... | 09/20/2011 |
| 8018778 | Memory read methods, apparatus, and systems Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values c... | 09/13/2011 |
| 8009482 | High temperature methods for enhancing retention characteristics of memory devices Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the ... | 08/30/2011 |
| 7978529 | Rewritable single-bit-per-cell flash memory Subject matter disclosed herein relates to multilevel flash memory, and more particularly to a method of changing a logic level of a single-bit-per-cell flash memory device multiple times before an erase operation. ... | 07/12/2011 |
| 7978530 | Correcting for over programming non-volatile storage A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line). ... | 07/12/2011 |
| 7978531 | Nonvolatile memory, verify method therefor, and semiconductor device using the nonvolatile memory Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construct... | 07/12/2011 |
| 7969788 | Charge loss compensation methods and apparatus Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking... | 06/28/2011 |
| 7965562 | Predictive programming in non-volatile memory In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming... | 06/21/2011 |
| 7940571 | Memory apparatus and method thereof for operating memory A memory apparatus and a method thereof for operating a memory are provided herein. The apparatus has the memory and a controller. The memory has a plurality of memory cells, and each the memory cells has a first side and the second side. Each of the first side and ... | 05/10/2011 |
| 7936609 | Memory controller, memory system, recording and reproducing method for memory system, and recording apparatus A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a pred... | 05/03/2011 |
| 7924626 | Efficient erase algorithm for SONOS-type NAND flash A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The meth... | 04/12/2011 |
| 7903468 | Adaptive dynamic reading of flash memories Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages... | 03/08/2011 |
| 7898870 | Nonvolatile memory device having a bit line select voltage generator adapted to a temperature change A bit line select voltage generator includes a first and second voltage generators and a voltage transmission unit. The first voltage generator operates to divide a reference voltage of a reference voltage generator to generate a first voltage and a second voltage, ... | 03/01/2011 |
| 7876622 | Read method for MLC Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of indiv... | 01/25/2011 |
| 7876621 | Adaptive dynamic reading of flash memories Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. A histogram is constructed by determining how many of some or all of the cells have threshold voltages in each of two or ... | 01/25/2011 |
| 7869283 | Method for determining native threshold voltage of nonvolatile memory A method for determining native threshold voltage of nonvolatile memory includes following steps. A memory cell including a control gate, a charge storage layer, a source region, and a drain region is provided. A programming operation is performed on the memory cell... | 01/11/2011 |
| 7864593 | Method for classifying memory cells in an integrated circuit A method for classifying memory cells in an integrated circuit is provided, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes determining, for each subset of the memory cells of a plurality of subsets o... | 01/04/2011 |
| 7859910 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array including a plurality of word lines; a parameter storage part which stores a parameter related to a programming voltage which is applied to a... | 12/28/2010 |
| 7852683 | Correcting for over programming non-volatile storage A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line). ... | 12/14/2010 |
| 7848152 | Method and system for adaptively finding reference voltages for reading data from a MLC flash memory A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, information about an initial threshold voltage distribution is firstly provided. A first threshold vo... | 12/07/2010 |
| 7839695 | High temperature methods for enhancing retention characteristics of memory devices Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the ... | 11/23/2010 |
| 7821838 | Method for erasing/programming/correcting a multi-level cell (MLC) A memory operating method includes the following steps. First, a memory including a charge storage structure is provided. Next, first type charges are injected into the charge storage structure such that a threshold level of the memory is higher than an erase level.... | 10/26/2010 |
| 7821839 | Gain control for read operations in flash memory A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M−1 read th... | 10/26/2010 |
| 7808833 | Method of operating an integrated circuit, integrated circuit and method to determine an operating point Embodiments of the present invention relate to a method to operate an integrated circuit that includes a memory. The memory encompasses a first and a second threshold level. The invention further relates to integrated circuits including a memory with a first and a s... | 10/05/2010 |
| 7791947 | Non-volatile memory device and methods of using The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed. ... | 09/07/2010 |
| 7787307 | Memory cell shift estimation method and apparatus Memory devices and methods are disclosed, such as those facilitating interpolation methods for reference memory cells based on their reference state and/or location in an array of memory cells. For example, a group of reference cells programmed to a subset of possib... | 08/31/2010 |
