Class 365/185.22 - Verify signal

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter under 185.2 including the use of any circuitry,
No. of patents: 1780
Last issue date: 05/14/2013

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
8441862	Program method of multi-bit memory device and data storage system using the same Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify vo...	05/14/2013
8441861	Self-check calibration of program or erase and verify process using memory cell distribution Apparatus and methods determine a program verify (PV) induced reading parameter distribution. A measured post-PV reading parameter distribution can be compared with an expected post-PV reading parameter distribution. For example, de-convolution can be applied to ide...	05/14/2013
8437197	Nonvolatile semiconductor memory and method of operating the same According to one embodiment, a nonvolatile semiconductor memory includes memory cells arranged in a memory cell array in the form of a matrix, the memory cell storing data having two or more levels associated with two or more threshold levels, respectively, a buffer...	05/07/2013
8432752	Adaptive write procedures for non-volatile memory using verify read A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A de...	04/30/2013
8422305	Method of programming nonvolatile memory device A method of programming a nonvolatile memory device includes inputting program data to page buffers; performing a program operation and a program verification operation until threshold voltages of memory cells included in a selected page reach a target level accordi...	04/16/2013
8411508	Automatic selective slow program convergence Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory...	04/02/2013
8400836	Segmented bitscan for verification of programming A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their ta...	03/19/2013
8395944	Method of operating semiconductor memory device A semiconductor memory device is operated by reading data stored in LSB and MSB pages of a first word line in response to a read command and storing the read data in first and second latches of a page buffer, outputting the data stored in the first latch externally ...	03/12/2013
8395945	Variable initial program voltage magnitude for non-volatile storage Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embo...	03/12/2013
8391073	Adaptive control of programming currents for memory cells A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the ...	03/05/2013
8391072	Semiconductor memory device and method for controlling the same According to one embodiment, a semiconductor memory device includes a plurality of memory cells, and a plurality of latch circuits. The memory cells are associated with columns and are capable of storing data. The latch circuits are associated with the columns and a...	03/05/2013
8391074	Semiconductor memory device and data write method thereof A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation ...	03/05/2013
8379456	Nonvolatile memory devices having dummy cell and bias methods thereof Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program o...	02/19/2013
8369155	Operating method in a non-volatile memory device A method of verifying a non-volatile memory device to increase the read margin even though a negative verifying voltage is not applied is disclosed. The method of verifying a non-volatile memory device includes coupling a cell string to a bit line precharged to a hi...	02/05/2013
8363479	Nonvolatile semiconductor memory device According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array connected to word lines and bit lines, and formed by arranging a plurality of memory cells in a matrix, each memory cell storing one of n values (n is a natural numbe...	01/29/2013
8363480	Nonvolatile semiconductor storage device A nonvolatile semiconductor storage device including a NAND cell unit having a first and a second select gate transistor, a plurality of memory cell transistors series connected between the first and second select gate transistors that are coupled to corresponding w...	01/29/2013
8355286	Method of operating nonvolatile memory device controlled by controlling coupling resistance value between a bit line and a page buffer A method of operating a nonvolatile memory device includes determining whether a program operation is performed on even memory cells coupled to even bit lines of a selected page, setting a coupling resistance value between odd bit lines of the selected page and page...	01/15/2013
8355287	Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then...	01/15/2013
8351270	Nonvolatile memory device and method of programming the device A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based ...	01/08/2013
8339861	Method and apparatus of performing an erase operation on a memory integrated circuit Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the ove...	12/25/2012
8335113	Flash memory and data erasing method of the same When data erasure of a flash memory is interrupted and restarted from the interrupted point, time required for the data erasure is shortened. A flash memory includes a memory cell(s), a verification circuit, and a power supply circuit. The verification circuit measu...	12/18/2012
8320187	Nonvolatile semiconductor memory and control method thereof According to one embodiment, a nonvolatile semiconductor memory includes memory cells storing data of multi-level, a bit scan circuit to scan the number of to-be-written memory cells and the number of memory cells that have passed the verify, a processing unit to pe...	11/27/2012
8315105	Method of erasing in non-volatile memory device An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory...	11/20/2012
8315104	Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a...	11/20/2012
8305817	Nonvolatile memory devices and program methods thereof in which a target verify operation and a pre-pass verify operation are performed simultaneously using a common verify voltage Provided are nonvolatile memory devices and program methods thereof. A nonvolatile memory device provides a program voltage to a selected word line and performs a program verify operation. The nonvolatile memory device controls a bit line voltage of the next program...	11/06/2012
8305816	Method of controlling a memory cell of non-volatile memory device A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-vo...	11/06/2012
8300474	Nonvolatile semiconductor memory According to one embodiment, a nonvolatile semiconductor memory includes a control circuit. The control circuit is configured to repeat an application of a write pulse and a verify read operation to a selected word line, perform a read operation from a selected memo...	10/30/2012
8289780	Page buffer, nonvolatile semiconductor memory device having the same, and program and data verification method A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal appli...	10/16/2012
8284611	Verifying and programming method of nonvolatile memory device A method of operating a nonvolatile memory device includes precharging bit lines coupled to strings, supplying a first verification voltage to a selected word line and supplying a pass voltage to word lines other than the selected word line, supplying a first sense ...	10/09/2012
8284612	Semiconductor memory device According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information ...	10/09/2012
8279679	Non-volatile semiconductor memory device, method of reading data therefrom, and semiconductor device A control circuit is configured to perform, in a write operation to a memory cell and a verify operation for verifying a threshold voltage of the memory cell, a voltage control to provide the memory cell with threshold voltage distributions. The circuit is configure...	10/02/2012
8279678	Method of performing program verification operation using page buffer of nonvolatile memory device A method of performing a program verification operation in a nonvolatile memory device includes storing program data, programmed into a selected memory cell of a memory cell block, in a page buffer which is coupled to a bit line of the memory cell block via a sense ...	10/02/2012
8274836	Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system A nonvolatile semiconductor memory device and a nonvolatile memory system having a unit which suppresses erroneous reading of a nonvolatile semiconductor memory device of a multi-level memory system are provided. In the nonvolatile semiconductor memory device and th...	09/25/2012
8270221	Nonvolatile memory device and method of operating the same A nonvolatile memory device includes a cell string, including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, and memory cells coupled in series between the drain select transistor and the source select tr...	09/18/2012
8238164	Method of programming nonvolatile memory device A method of programming a nonvolatile memory device comprises applying a gradually increasing program voltage to a memory cell, determining the number of verify voltages to be applied to the memory cell during a program loop based on the change of a threshold voltag...	08/07/2012
8238163	Nonvolatile memory device A page buffer of a nonvolatile memory device according to the present disclosure comprises a first data latch unit configured to store data for program or program inhibition, a second data latch unit configured to store data for setting threshold voltage states of c...	08/07/2012
8233327	Method of programming nonvolatile memory device A method of programming a nonvolatile memory device comprises a bit line voltage set-up step of receiving a program command and data to be programmed and setting up a voltage of a selected bit line according to a state of program data; a program step of supplying a ...	07/31/2012
8228740	Method of operating nonvolatile memory device A nonvolatile memory device is operated by, inter alia, performing a program operation on memory cells belonging to a page selected from among a plurality of pages, performing a verification operation on the programmed memory cells, loading a start loop value of a f...	07/24/2012
8228741	Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by dela...	07/24/2012
8223558	Nonvolatile semiconductor memory device A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, ...	07/17/2012

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Bizarre Patents

PatentStorm News

Class 365/185.22 - Verify signal