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| Number | Title | Issue Date |
| 8189392 | Page buffer circuit A page buffer circuit comprises a first sensing unit configured to sense a voltage of a bit line and change a voltage of a first sense node, a data conversion unit configured to sense a voltage level of the first sense node and change a voltage level of a second sen... | 05/29/2012 |
| 8174898 | Sense amplifier and data sensing method thereof A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing th... | 05/08/2012 |
| 8169831 | High speed sense amplifier array and method for non-volatile memory Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an ... | 05/01/2012 |
| 8169830 | Sensing for all bit line architecture in a memory device Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the... | 05/01/2012 |
| 8164961 | Nonvolatile semiconductor memory device which can electrically rewrite data and system therefor A nonvolatile semiconductor memory device includes a memory cell, latch circuits, and an arithmetic operation circuit. The memory cell stores data by a difference in threshold voltage. A read operation is performed twice or more on the memory cell under the same rea... | 04/24/2012 |
| 8164958 | Memory apparatus and method for operating the same The invention provides a method for reading a first data storage of a memory cell. The method comprises sensing a first current of the memory cell by applying a first bit line voltage on the memory cell. When the first current is larger than a first reference curren... | 04/24/2012 |
| 8154928 | Integrated flash memory systems and methods for load compensation Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the lo... | 04/10/2012 |
| 8149627 | Current sink system based on sample and hold for source side sensing Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current ... | 04/03/2012 |
| 8144525 | Memory cell sensing using negative voltage Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage t... | 03/27/2012 |
| 8125831 | Sensing against a reference cell Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include pr... | 02/28/2012 |
| 8120964 | Nonvolatile memory device and method of operating the same A nonvolatile memory device includes a first node, a current source configured to have a current value determined according to a voltage supplied to the first node, and a memory cell string coupled to the first node, the memory cell string including at least one mem... | 02/21/2012 |
| 8120965 | Data storage device and data read method The invention provides a data read method. First, a training sequence stored in a storage unit of a memory is read according to at least one sense voltage to obtain a read-out training sequence. Whether the read-out training sequence is correct is then determined. W... | 02/21/2012 |
| 8116151 | Multi-level storage algorithm to emphasize disturb conditions Providing systems and methods that reduce memory device read errors and improve memory device reliability by intelligently disturbing the memory cells during storage of their characteristic states. A specification component can determine a desired characteristic sta... | 02/14/2012 |
| 8098526 | Reverse reading in non-volatile memory with compensation for coupling Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the e... | 01/17/2012 |
| 8085597 | Nonvolatile semiconductor memory and data writing method for nonvolatile semiconductor memory A method having the steps of applying the same gate voltage to each of gate terminals of a plurality of memory cells via word lines to designate the memory cells as a write target, and simultaneously applying a write voltage that corresponds to each write data acros... | 12/27/2011 |
| 8077521 | Bitline current generator for a non-volatile memory array and a non-volatile memory array A bitline current generator, for a non-volatile memory array which comprises a plurality of memory bitcells and bitlines, comprises a switching means for each bitline for coupling a bitline to a program voltage supply when the bitline is selected for programming and... | 12/13/2011 |
| 8077522 | Memory and method operating the memory A memory comprises a memory array, a sense unit, and a biasing and shielding circuit. The biasing and shielding circuit is coupled to the memory array and the sense unit, wherein the biasing and shielding circuit comprises a first transistor, a second transistor, an... | 12/13/2011 |
| 8068369 | Sense amplifier circuit and semiconductor memory device A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between t... | 11/29/2011 |
| 8064263 | Current sink system for source-side sensing Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current ... | 11/22/2011 |
| 8059468 | Switched bitline VTH sensing for non-volatile memories A transistor provides a voltage source commonly switched by SE and SO switches to pre-charge both the even bitline and the odd bitline. The SE and SO switches are open during a sensing stage to determine whether the cell side or the reference side has a higher curre... | 11/15/2011 |
| 8050100 | Non-volatile semiconductor memory device with a sense amplifier reference circuit having a MONOS transfer transistor A non-volatile semiconductor memory device includes a sense amplifier, first and second bit lines that are connected to the sense amplifier, a first memory cell column that is connected to the first bit line, the first memory cell column being formed by a plurality ... | 11/01/2011 |
| 8045391 | Non-volatile memory and method with improved sensing having bit-line lockout control In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-se... | 10/25/2011 |
| 8045390 | Memory system with dynamic reference cell and method of operating the same A system for operating a memory device includes a memory array having a number of memory cells and a set of dynamic reference cells coupled to the memory cells in word lines. Each of the dynamic reference provides the associated memory cells with a dynamic reference... | 10/25/2011 |
| 8040734 | Current-mode sense amplifying method A sense amplifying method, applied in a memory having a memory cell and a reference cell, includes: charging the memory cell and the reference cell to have a cell current and a reference current, respectively; duplicating the cell current and the reference current t... | 10/18/2011 |
| 8036041 | Method for non-volatile memory with background data latch caching during read operations Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to per... | 10/11/2011 |
| 8027201 | Nonvolatile memory device with load-free wired-or structure and an associated driving method A nonvolatile semiconductor memory device includes an internal output line, and a page buffers. Each page buffer is coupled to at least one bitline, the internal output line, and a data input line physically distinct from the internal output line, and configured to ... | 09/27/2011 |
| 8023333 | Reading method for MLC memory and reading circuit using the same A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the ... | 09/20/2011 |
| 8004902 | Nonvolatile semiconductor memory device A nonvolatile memory device includes a memory cell that stores data by presence or absence of electrons accumulated in a floating gate, a read reference current generator that generates a read reference current for reading data from the memory cell based on a consta... | 08/23/2011 |
| 8004903 | Semiconductor memory device A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense a... | 08/23/2011 |
| 8004901 | Semiconductor device and method for controlling A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells that are provided in a matrix and that have a charge storage layer made of an insulating film that is provided on a semiconductor substrate and a plurality of word lin... | 08/23/2011 |
| 7995397 | Power supply tracking single ended sensing scheme for SONOS memories A SONOS memory sensing scheme includes a reference current circuit that tracks the changes in the power supply (Vcc). An equalizer of the current sense amplifier is coupled between the read out current line and the reference current line. The current sense amplifier... | 08/09/2011 |
| 7995398 | Structures and methods for reading out non-volatile memories Non-differential sense amplifier circuitry for reading out Non-Volatile Memories (NVMs) and its operating methods are disclosed. Such non-differential amplifier circuitry requires exceptionally low power and achieves moderate sensing speed, as compared to a conventi... | 08/09/2011 |
| 7983089 | Sense amplifier with capacitance-coupled differential sense amplifier During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantial... | 07/19/2011 |
| 7978526 | Low noise sense amplifier array and method for nonvolatile memory In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the lo... | 07/12/2011 |
| 7978525 | Data flow scheme for low power DRAM Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determ... | 07/12/2011 |
| 7974134 | Voltage generator to compensate sense amplifier trip point over temperature in non-volatile memory In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared ... | 07/05/2011 |
| 7974133 | Robust sensing circuit and method A sense amplifier is disclosed. One embodiment is a sensing circuit that includes a sensing device and a sense transistor coupled to the sensing device. A first switch that is coupled to the sense transistor and to the sensing device causes the sensing device to be ... | 07/05/2011 |
| 7965560 | Non-volatile memory with power-saving multi-pass sensing A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing veri... | 06/21/2011 |
| 7965559 | Systems and methods for improved floating-gate transistor programming The present invention describes systems and methods for improving the programming of floating-gate transistors. An exemplary embodiment of the present invention provides a floating-gate transistor programming system including an array of floating-gate transistors an... | 06/21/2011 |
| 7961521 | Sensing circuit for flash memory device operating at low power supply voltage A sensing circuit that operates even at a low power supply voltage and reduces stress on a memory cell in a flash memory device without lowering a reading speed at the low power supply voltage is provided. The sensing circuit includes a first load element, a first i... | 06/14/2011 |
