Class 365/185.2 - Reference signal (e.g., dummy cell)

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter under 185.18 wherein a data signal on the
No. of patents: 1028
Last issue date: 04/10/2012

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Number	Title	Issue Date
8154927	Nonvolatile memory device and nonvolatile memory system employing same A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in ser...	04/10/2012
8144538	Semiconductor device A semiconductor device to improve layout uniformity may include an active region formed in a substrate, a dummy active region formed in the substrate and separated from the active region, a word line crossing over the active region, and a dummy word line. The dummy ...	03/27/2012
8134873	Flash memory device and programming/erasing method of the same A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor...	03/13/2012
8130584	Semiconductor device and control method of the same The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10...	03/06/2012
8107297	Method of reading nonvolatile memory device and method of operating nonvolatile memory device A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a ...	01/31/2012
8089813	Controllable voltage reference driver for a memory system A voltage reference driver includes a voltage divider circuit with a voltage reference output node to output a voltage between a first voltage and a second voltage. The voltage reference driver also includes a first selectable impedance circuit coupled to a node at ...	01/03/2012
8089812	Semiconductor memory device A semiconductor memory device can reduce a circuit area necessary for row repair. The semiconductor memory device includes a plurality of memory banks, a plurality of cell arrays arranged in each of the memory banks, a plurality of array word lines arranged in each ...	01/03/2012
8077520	Determining threshold voltage distribution in flash memory Methods, apparatuses, and systems for comparing threshold voltages of a plurality of flash memory cells to a plurality of reference voltages. A number of flash memory cells having threshold voltages that fall within each bin of a plurality of bins is determined. The...	12/13/2011
8072815	Array of non-volatile memory cells including embedded local and global reference cells and system An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a lo...	12/06/2011
8068367	Reference current sources Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical conductor. The reference current source may include a current mirror w...	11/29/2011
8068368	Method of performing read operation in flash memory device A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected pa...	11/29/2011
8064262	Semiconductor device and method using stress information A semiconductor device in accordance with one embodiment of the invention can include a first data storage region including a non-volatile main data storage region. Additionally, the semiconductor device can include a second data storage region including a non-volat...	11/22/2011
8045388	Semiconductor device and control method of the same The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10...	10/25/2011
8045389	Semiconductor memory device A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect...	10/25/2011
8040733	Non-volatile memory device and method of operating the same A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to c...	10/18/2011
8036040	Memory system with improved efficiency of data transfer between host, buffer, and nonvolatile memory The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response...	10/11/2011
8031527	Semiconductor device and method for adjusting reference levels of reference cells A semiconductor device includes a first reference cell used for programming or reading non-volatile memory cells, and an adjustment circuit adjusting a first reference level of the first reference cell when the first reference level is changed. ...	10/04/2011
8023332	Cell deterioration warning apparatus and method Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicat...	09/20/2011
8018773	Array of non-volatile memory cells including embedded local and global reference cells and system An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a lo...	09/13/2011
8014207	Nonvolatile memory device and method of operating the same A nonvolatile memory device includes an encoder configured to perform a scramble operation on input data, a digital sum value (DSV) generator configured to generate a DSV indicating a difference between a number of data ‘0’ and a number of data ‘1’ in the in...	09/06/2011
7995396	Methods of operating memory devices Provided are methods of operating NAND nonvolatile memory devices. The operating methods include applying a read voltage or a verify voltage to a selected memory cell from among a plurality of memory cells of a cell string to verify or read a programmed state of the...	08/09/2011
7978524	Semiconductor device A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first ...	07/12/2011
7978522	Flash memory device including a dummy cell A non-volatile memory device includes a selection transistor coupled to a bit line. The device also includes a plurality of memory cells serially coupled to the selection transistor and at least one dummy cell located between the plurality of memory cells. The dummy...	07/12/2011
7978523	Semiconductor device and control method of the same The present invention provides a semiconductor memory and a control method therefore, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10	07/12/2011
7974131	Nonvolatile memory comprising a circuit capable of memory life time recognizing A nonvolatile memory wherein remaining lifetimes of memory cells can be accurately determined is provided, the nonvolatile memory includes: plural memory cell groups, assigned with respective addresses, arranged for respective words and used for storing one word of ...	07/05/2011
7974130	Semiconductor memory device and method for erasing the same A semiconductor memory device including a memory cell array with NAND cell units arranged therein, the NAND cell unit having a plurality of electrically rewritable and non-volatile memory cells connected in series, first and second select gate transistors disposed f...	07/05/2011
7974132	Shifting reference values to account for voltage sag A system and method, including software implemented techniques, can be used to adjust for sag in stored data values. Charge is applied to multiple memory cells, and each memory cell is charged to a target voltage corresponding to a data value. The memory cells inclu...	07/05/2011
7969787	Semiconductor device and control method of the same The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10...	06/28/2011
7961519	Memory employing independent dynamic reference areas A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch componen...	06/14/2011
7961520	Encoding and decoding to reduce switching of flash memory transistors Methods of encoding data to and decoding data from flash memory devices are provided. User data having an unknown ratio of 1's to 0's is received. The user data is utilized in generating transformed data that has a predictable ratio of 1's to 0's. The transformed da...	06/14/2011
7944753	Electrically erasable programmable read-only memory (EEPROM) cell and methods for forming and reading the same In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than t...	05/17/2011
7940570	Memory employing separate dynamic reference areas A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data a...	05/10/2011
7924622	Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermin...	04/12/2011
7924623	Method for memory cell erasure with a programming monitor of reference cells Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a nu...	04/12/2011
7920428	Methods and apparatuses relating to automatic cell threshold voltage measurement Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells and a bit line pre-charge reference circuit. If the reference curren...	04/05/2011
7916546	Methods for programming a memory device and memory devices using inhibit voltages that are less than a supply voltage Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less than a supply voltage. The word lines of memory cells to be programmed are biased at a programming prepara...	03/29/2011
7898889	Nonvolatile semiconductor memory device A memory includes first selective transistors connected between one end of cell strings and bit lines; second selective transistors connected between the other end of the cell strings and a cell source line; a dummy cell string; a first dummy selective transistor co...	03/01/2011
7898866	Nonvolatile memory device and method of operating the same A nonvolatile memory device includes a first plane and a second plane, an address decoder configured to decode an externally input address and to output a first plane select signal and a second plane select signal for enabling any one of the first and second planes,...	03/01/2011
7898867	Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory...	03/01/2011
7898865	Method of reading nonvolatile memory device and method of operating nonvolatile memory device A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a ...	03/01/2011

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Class 365/185.2 - Reference signal (e.g., dummy cell)