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| Number | Title | Issue Date |
| 8184483 | Nonvolatile memory device and method of programming the same A nonvolatile memory device includes a memory cell array, including a first memory cell group configured to store data and a second memory cell group configured to store operation information, including first and second program start voltages, a page buffer unit, in... | 05/22/2012 |
| 8184484 | Semiconductor memory device including stacked gate having charge accumulation layer and control gate and method of writing data to semiconductor memory device A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of... | 05/22/2012 |
| 8179726 | Method and apparatus for programming flash memory A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array usi... | 05/15/2012 |
| 8174894 | Program method of flash memory device A program method of a flash memory device includes inputting a first data and a second data to a page buffer coupled to memory cells including an even page and an odd page, pre-programming a first memory cell of the odd page using the first data, programming a secon... | 05/08/2012 |
| 8174895 | Programming non-volatile storage with fast bit detection and verify skip A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. ... | 05/08/2012 |
| 8174897 | Programming in a memory device Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses wher... | 05/08/2012 |
| 8174896 | Nonvolatile memory device and method of operating the same A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference v... | 05/08/2012 |
| 8149625 | Nonvolatile memory device, operating method thereof, and memory system including the same A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of memory cells in the memory cell array; and control logic configured to adjust an initial voltage of the st... | 04/03/2012 |
| 8149624 | Method and apparatus for reducing read disturb in memory Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. ... | 04/03/2012 |
| 8149626 | Threshold voltage digitizer for array of programmable threshold transistors A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of transistors, wherein the ramp voltage is configured to increase base... | 04/03/2012 |
| 8139419 | Programming methods and memories Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying a set of incrementing program pulses to program a selected cell to a first target threshold voltage, and ... | 03/20/2012 |
| 8130551 | Extra dummy erase pulses after shallow erase-verify to avoid sensing deep erased threshold voltage An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify operation. The verify operation uses a verify level which is offset higher ... | 03/06/2012 |
| 8120963 | Method and system for program pulse generation during programming of nonvolatile electronic devices Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorith... | 02/21/2012 |
| 8116140 | Saw-shaped multi-pulse programming for program noise reduction in memory In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate... | 02/14/2012 |
| 8111555 | NAND step voltage switching method Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment ... | 02/07/2012 |
| 8111554 | Starting program voltage shift with cycling of non-volatile memory A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs... | 02/07/2012 |
| 8085596 | Reducing noise in semiconductor devices The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes ... | 12/27/2011 |
| 8081517 | Solid state storage system for uniformly using memory area and method controlling the same A solid state storage system includes a memory area having a plurality of pages and is capable of storing program information about each page. The memory area stores the number of pulse counts applied to each page. A main memory controller receives the program infor... | 12/20/2011 |
| 8077519 | Programming a memory device to increase data reliability Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is deter... | 12/13/2011 |
| 8064261 | Semiconductor nonvolatile memory device An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing ... | 11/22/2011 |
| 8059467 | Memory device and memory programming method Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal ... | 11/15/2011 |
| 8045387 | Nonvolatile memory device and program method with improved pass voltage window A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a hig... | 10/25/2011 |
| 8023331 | Semiconductor memory device including stacked gate having charge accumulation layer and control gate and method of writing data to semiconductor memory device A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of... | 09/20/2011 |
| 8023330 | Method of erasing a nonvolatile memory device In a method of erasing a nonvolatile memory device, an erase operation is performed on memory cells of a selected block. A first soft program operation is performed on the cells on which the erase operation has been performed. The erase operation and the first soft ... | 09/20/2011 |
| 8014206 | Threshold voltage digitizer for array of programmable threshold transistors An integrated circuit including a voltage generator and a control module. The voltage generator is configured to generate a first voltage based on a plurality of codewords, and output the first voltage to a first word line communicating with a first set of transisto... | 09/06/2011 |
| 8004900 | Controlling select gate voltage during erase to improve endurance in non-volatile memory A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are dr... | 08/23/2011 |
| 8000149 | Non-volatile memory device The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cel... | 08/16/2011 |
| 7995395 | Charge loss compensation during programming of a memory device A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells ... | 08/09/2011 |
| 7995393 | Flash memory device and system including the same The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a selected memory block of the flash memory device; and determining the selected memory block or the flash me... | 08/09/2011 |
| 7995394 | Program voltage compensation with word line bias change to suppress charge trapping in memory Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at ... | 08/09/2011 |
| 7990771 | Program method of flash memory device A method of erasing and programming a flash memory device including multi-level cells (MLCs). MLCs of a word line are selected and some of the MLCs are pre-programmed based on whether their individual threshold voltages are included in a first voltage range. The sel... | 08/02/2011 |
| 7983088 | Programming in a memory device Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of prog... | 07/19/2011 |
| 7978521 | Memory device and method of programming thereof The method of programming data in a memory device includes applying a plurality of pulses to a plurality of memory cells, at least one of the plurality of pulses being a positive pulse having a positive voltage and at least one of the plurality of pulses being a neg... | 07/12/2011 |
| 7978520 | Compensation of non-volatile memory chip non-idealities by program pulse adjustment To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude d... | 07/12/2011 |
| 7974129 | Method and apparatus for programming flash memory A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array usi... | 07/05/2011 |
| 7969785 | Low voltage non-volatile memory with charge trapping layer Methods, circuits, processes, devices, and/or arrangements for a non-volatile memory (NVM) cell operable at relatively low voltages are disclosed. In one embodiment, an NVM cell can include: (i) a gate over a charge trapping layer, the charge trapping layer being in... | 06/28/2011 |
| 7969786 | Method of programming nonvolatile memory device A method of programming nonvolatile memory devices. A program operation is performed by applying a dummy program pulse having a pulse width wider than a pulse width of a program start pulse. A program operation is performed by applying the program start pulse. It is... | 06/28/2011 |
| 7965558 | Methods and circuits for generating a high voltage and related semiconductor memory devices Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the rampin... | 06/21/2011 |
| 7948802 | Sensing memory cells The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment... | 05/24/2011 |
| 7929350 | Nonvolatile memory device, operating method thereof, and memory system including the same A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of memory cells in the memory cell array; and control logic configured to adjust an initial voltage of the st... | 04/19/2011 |
