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"During my service in the United States Congress, I took the initiative in creating the Internet."
Al Gore ; The basis for the later misquote by US Republicans that Gore had "invented" the Internet. Gore was the leading political champion of the modern-day Internet.
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| Number | Title | Issue Date |
| 8184482 | Nonvolatile memory device for preventing a source line bouncing phenomenon A nonvolatile memory device includes a memory cell array configured to include cell strings coupled between respective bit lines and a source line, a unilateral element coupled to the source line, and a negative voltage generation unit coupled to the unilateral elem... | 05/22/2012 |
| 8179725 | Programming rate identification and control in a solid state memory Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory... | 05/15/2012 |
| 8174893 | Independent well bias management in a memory device Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one s... | 05/08/2012 |
| 8169828 | Semiconductor memory cell, method for manufacturing the same and method for operating the same A semiconductor memory cell, and method of manufacturing a semiconductor memory cell and an method of operating a semiconductor memory cell. A method of operating may include programming a semiconductor memory cell by applying a preset programming voltage to a commo... | 05/01/2012 |
| 8169829 | Memory controller, memory system, recording and reproducing method for memory system, and recording apparatus A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a pred... | 05/01/2012 |
| 8159881 | Reference voltage optimization for flash memory A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is... | 04/17/2012 |
| 8149623 | Controller and non-volatile semiconductor memory device A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels, an ... | 04/03/2012 |
| 8149622 | Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage A memory system includes a NAND flash memory, a NOR flash memory and a SRAM memory on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins ... | 04/03/2012 |
| 8144517 | Multilayered nonvolatile memory with adaptive control A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, whe... | 03/27/2012 |
| 8144518 | Semiconductor device The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of ... | 03/27/2012 |
| 8139418 | Techniques for controlling a direct injection semiconductor memory device Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a direct injection semiconductor memory device. The method may comprise applyi... | 03/20/2012 |
| 8125830 | Area-efficient electrically erasable programmable memory cell Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of t... | 02/28/2012 |
| 8120961 | Nonvolatile semiconductor memory device A stacked body with a plurality of dielectric films and electrode films alternately stacked therein is provided. The electrode film is divided into a plurality of control gate electrodes extending in one direction. The stacked body is provided with a U-pillar penetr... | 02/21/2012 |
| 8116138 | Memory device distributed controller system A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave con... | 02/14/2012 |
| 8116139 | Bit line stability detection A power supply and monitoring apparatus such as in a nonvolatile memory system. A power supply circuit provides power to a large number of sense modules, each of which is associated with a bit line and a string of non-volatile storage elements. During a sensing oper... | 02/14/2012 |
| 8107296 | Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation o... | 01/31/2012 |
| 8107295 | Nonvolatile memory device and read method thereof An object of the present inventive concept is providing a nonvolatile memory device having improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device according to the present inventive concept includes a memor... | 01/31/2012 |
| 8102714 | Programming methods for multi-level memory devices A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least... | 01/24/2012 |
| 8102713 | Non-volatile memory monitor The invention provides circuits, systems, and methods for monitoring a non-volatile memory (NVM) cell, or an array of NVM cells. The monitor is capable of switching from a normal operating state to an evaluation state, monitoring for one or more particular character... | 01/24/2012 |
| 8102715 | Power-off apparatus, systems, and methods Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to ge... | 01/24/2012 |
| 8094502 | Write-precompensation and variable write backoff A technique for writing data is disclosed. The technique includes estimating an amount of additional voltage on a victim cell of a solid-state storage device caused by writing to one or more other cells in the solid-state storage device, determining a modified write... | 01/10/2012 |
| 8094503 | Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-cha... | 01/10/2012 |
| 8085594 | Reading technique for memory cell with electrically floating body transistor A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a s... | 12/27/2011 |
| 8085595 | Nonvolatile memory devices and methods of controlling the wordline voltage of the same A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wor... | 12/27/2011 |
| 8081516 | Method and apparatus to suppress fringing field interference of charge trapping NAND memory With advanced lithographic nodes featuring a half-pitch of 30 nm or less, charge trapping NAND memory has neighboring cells sufficiently close together that fringing fields from a neighboring pass gate interferes with the threshold voltage. The interference results ... | 12/20/2011 |
| 8081515 | Trench monos memory cell and array The MONOS vertical memory cell of the present invention allow miniaturization of the memory cell area. The two embodiments of split gate and single gate provide for efficient program and erase modes as well as preventing read disturb in the read mode. ... | 12/20/2011 |
| 8072814 | NAND with back biased operation Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drive... | 12/06/2011 |
| 8072813 | Method and apparatus for programming nonvolatile memory A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets... | 12/06/2011 |
| 8064260 | Power supplies in flash memory devices and systems Power supplies in flash memory devices are disclosed. A first section of a flash memory device includes non-volatile memory for storing data. A second section of the flash memory device includes at least first and second pumping circuits. The first pumping circuit r... | 11/22/2011 |
| 8059466 | Memory system and programming method thereof Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell ... | 11/15/2011 |
| 8059463 | Method for generating soft bits in flash memories Information stored as physical states of cells of a memory is read first by setting each of one or more references to a respective member of a first set of values and reading the physical states of the cells relative to the values of the first set. Subsequently, the... | 11/15/2011 |
| 8059464 | Nonvolatile memory device, methods of programming the nonvolatile memory device and memory system including the same A nonvolatile memory device is provided. A counter counts an amount of data to be program-inhibited among data to be written to memory cells to provide a first count value. The counter also counts an amount of program-inhibited data among data written to the memory ... | 11/15/2011 |
| 8059465 | Non-volatile semiconductor memory device When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instr... | 11/15/2011 |
| 8054690 | Non-volatile memory and semiconductor device There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injec... | 11/08/2011 |
| 8054689 | Memory card using multi-level signaling and memory system having the same A memory card including a memory controller, a memory system and a method to control a memory are provided. The memory card includes a flash memory, a memory interface outputting a writing data signal to be written into the flash memory, and a multi-level converter ... | 11/08/2011 |
| 8050098 | Program method of nonvolatile memory device A program method of nonvolatile memory devices, which can solve an under program problem by preventing a drop of a verify voltage in the program, and verify operations. According to an aspect of the method, a program operation is performed on a selected memory cell ... | 11/01/2011 |
| 8050097 | Method of programming nonvolatile memory device According to an aspect of a method of programming a nonvolatile memory device, a first program operation command is input, and a program operation is executed according to a program start voltage stored in a program start voltage storage unit. Here, a program voltag... | 11/01/2011 |
| 8050099 | Apparatus for generating a voltage and non-volatile memory device having the same An apparatus for generating a voltage includes a first voltage outputting circuit configured to receive an input voltage and adjust and output a first voltage in accordance with a temperature, a buffer circuit configured to receive the first voltage and output the r... | 11/01/2011 |
| 8045386 | Methods and apparatus for programming a memory cell using one or more blocking memory cells Methods and apparatus for programming a memory cell using one or more blocking memory cells facilitate mitigation of capacitive voltage coupling. The methods include applying a program voltage to a selected memory cell of a string of memory cells, and applying a cut... | 10/25/2011 |
| 8040730 | Nonvolatile memory device A nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to control reading and programming operations for reading data from and inputting data to the memory cell array, respectively. The control circuit includes first ... | 10/18/2011 |
