Class 365/185.17 - Logic connection (e.g., NAND string)

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter under 185.05 wherein the floating gate elements
No. of patents: 1433
Last issue date: 05/29/2012

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Number	Title	Issue Date
8189391	Non-volatile semiconductor storage device including a control circuit A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the oth...	05/29/2012
RE43417	Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings undergoing programming operations with significant variations in potential. ...	05/29/2012
8184481	Memory devices and methods of their operation including selective compaction verify operations Memory devices and methods of their operation, where following an erasure of a string of memory cells, a selective compaction verify operation is performed on one or more, but less than all, of the memory cells of the string, and, if the selective compaction verify ...	05/22/2012
8179724	Sensing for memory read and program verify operations in a non-volatile memory device Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cel...	05/15/2012
8179723	Non-volatile memory with boost structures A non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually disch...	05/15/2012
8174892	Increased NAND flash memory read throughput A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from dif...	05/08/2012
8174889	Programming memory devices A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is d...	05/08/2012
8174891	Non-volatile semiconductor memory device and method of writing data in non-volatile semiconductor memory devices A non-volatile semiconductor memory device includes a NAND cell unit including a plurality of electrically rewritable non-volatile memory cells serially connected. The NAND cell unit has one end connected to a bit line via a first selection gate transistor and the o...	05/08/2012
8174890	Non-volatile semiconductor storage device A memory cell array has plural memory strings arranged therein, each of which including a plurality of electrically-rewritable memory transistors and selection transistors. Each memory string includes a body semiconductor layer including four or more columnar portio...	05/08/2012
8169827	NAND flash memory string apparatus and methods of operation thereof A NAND string, its operation, and manufacture is described herein. The NAND string includes one or more memory cells, a first selection transistor coupled to the memory cells, and a second selection transistor coupled between the memory cell and the first selection ...	05/01/2012
8164955	NOR flash memory device and method for fabricating the same Embodiments of a NOR flash memory and method for fabricating the same are provided. Bit lines can be formed as self-aligned source and drain regions between adjacent first polysilicon patterns. Contacts for the source and drain regions can be provided according to b...	04/24/2012
8164957	Reducing energy consumption when applying body bias to substrate having sets of nand strings Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bia...	04/24/2012
8164956	Non-volatile semiconductor storage device At least some of the memory transistors included in a first memory string are commonly connected to first conductive layers that are connected to at least some of the memory transistors included in a second memory string connected to the same third and fourth conduc...	04/24/2012
8159880	NAND flash memory In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the me...	04/17/2012
8159879	Reducing effects of program disturb in a memory device A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass vo...	04/17/2012
8154926	Memory cell programming One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states. Such embodiments include programming, separately, the first cell to one of a third number of states based...	04/10/2012
8139417	Flash memory device and read method A flash memory device includes a word line decoder configured to receive a row address, and decode a selected word line and a neighboring non-selected word line corresponding to the row address during a read operation, and a word line driver configured to receive da...	03/20/2012
8116135	Non-volatile memory cell read failure reduction The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a sele...	02/14/2012
8116137	Memory cell operation Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at leas...	02/14/2012
8102712	NAND programming technique A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided column-stripe (CS2) data pattern. The CS2 data pattern comprises a mem...	01/24/2012
8089811	Flash memory devices with memory cells strings including dummy transistors with selective threshold voltages Flash memory devices include a first memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to a bit line and a second memory cell...	01/03/2012
8081513	NAND flash memory A NAND flash memory has a control circuit. The control circuit applies a writing voltage between a control gate and a well by applying a first voltage to the well and a positive second voltage higher than the first voltage to the control gate during the writing oper...	12/20/2011
8081514	Partial speed and full speed programming for non-volatile memory using floating bit lines Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partia...	12/20/2011
8077518	E/P durability by using a sub-range of a full programming range A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the v...	12/13/2011
8072812	Sensing of memory cells in NAND flash An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed thre...	12/06/2011
8072811	NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device...	12/06/2011
8068366	Analog read and write paths in a solid state memory device A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge correspo...	11/29/2011
8059462	Nonvolatile semiconductor memory device The nonvolatile semiconductor memory device related to an embodiment of the present invention includes a cell array including a memory string, a bit line connected to the memory string, a first wire connected to a cell source line of a memory cell, a second wire con...	11/15/2011
8054688	Non-volatile memory device and erase method Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines conn...	11/08/2011
8050096	Programming method to reduce gate coupling interference for non-volatile memory A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of t...	11/01/2011
8045384	Reduced programming pulse width for enhanced channel boosting in non-volatile storage Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter duration, partway through the programming operation. A switchover point can ...	10/25/2011
8045385	Methods of operating nonvolatile memory devices to inhibit parasitic charge accumulation therein Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing even-numbered nonvolatile memory cells in the first string and then selectively erasing the odd-numbered nonvol...	10/25/2011
8045383	Non-volatile memory devices including dummy word lines and related structures and methods A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a firs...	10/25/2011
8027200	Reduction of quick charge loss effect in a memory device Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being...	09/27/2011
8023327	Non-volatile semiconductor memory device A memory device including a NAND string with multiple memory cells connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, whe...	09/20/2011
8018771	Fast programming memory device In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being con...	09/13/2011
8009477	Integrated circuit and method of forming an integrated circuit An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a d...	08/30/2011
8000146	Applying different body bias to different substrate portions for non-volatile storage Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bia...	08/16/2011
8000145	Method for programming nand type flash memory Disclosed is a method for programming a flash memory device capable of preventing a threshold voltage distribution of a memory cell from being moved due to a pass disturbance of the memory cell programmed initially at a program operation performed on a page-unit bas...	08/16/2011
7995391	Multiple select gates with non-volatile memory cells Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array i...	08/09/2011

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Class 365/185.17 - Logic connection (e.g., NAND string)