A hand wearable body squeegee comprising a glove portion, a concave squeegee band, and a linear squeegee band.
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| Number | Title | Issue Date |
| 8437183 | Auxiliary parity bits for data written in multi-level cells Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where... | 05/07/2013 |
| 8422289 | Fabrication method of nanoparticles by chemical curing A method of producing nanoparticles by using chemical curing. The method includes depositing a metal thin film on a substrate, applying an insulator precursor on a metal thin film, and adding a curing agent and a catalyst to the insulator precursor to perform the ch... | 04/16/2013 |
| 8391060 | Nonvolatile memory and semiconductor device A nonvolatile memory capable of acting at each 1 bit and having a high integration density. A small-sized semiconductor device of multiple high functions having such nonvolatile memory. The nonvolatile memory is constructed to have a memory cell composed of two memo... | 03/05/2013 |
| 8351254 | Semiconductor device The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transis... | 01/08/2013 |
| 8351255 | Semiconductor device p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data ... | 01/08/2013 |
| 8325516 | Semiconductor device with split gate memory cell and fabrication method thereof A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate i... | 12/04/2012 |
| 8284599 | Nonvolatile memory device and related programming method A method of programming a nonvolatile memory device comprises programming memory cells connected to a first wordline, programming memory cells connected to a second wordline, programming memory cells connected to a third line between the first wordline and the secon... | 10/09/2012 |
| 8243510 | Non-volatile memory cell with metal capacitor According to one exemplary embodiment, a memory cell in a semiconductor chip includes a non-volatile memory transistor, a control gate, and a floating gate. The control gate is capacitively coupled to the floating gate of the non-volatile memory transistor by a meta... | 08/14/2012 |
| 8228726 | N-channel SONOS non-volatile memory for embedded in logic A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least on... | 07/24/2012 |
| 8213227 | 4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes t... | 07/03/2012 |
| 8208296 | Apparatus and method for extended nitride layer in a flash memory A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the ins... | 06/26/2012 |
| 8208297 | Integrated circuits to control access to multiple layers of memory in a solid state drive Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in mult... | 06/26/2012 |
| 8194445 | Semiconductor storage device comprising dot-type charge accumulation portion and control gate, and method of manufacturing the same A semiconductor memory device includes a first insulation film, Charge accumulation portions, a second insulation film, and a control gate. The first insulation film is located on an active area (AA). The charge accumulation portions comprise minute crystals arrange... | 06/05/2012 |
| 8189377 | Semiconductor device p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data ... | 05/29/2012 |
| 8130571 | Semiconductor integrated circuit A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory are... | 03/06/2012 |
| 8077511 | Hybrid non-volatile memory A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provi... | 12/13/2011 |
| 7990762 | Integrated circuits to control access to multiple layers of memory Circuits to control access to memory; for example, third dimension memory are provided. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multi... | 08/02/2011 |
| 7978545 | Semiconductor integrated circuit A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory are... | 07/12/2011 |
| 7961510 | Integrated circuits to control access to multiple layers of memory in a solid state drive Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in mult... | 06/14/2011 |
| 7940561 | Semiconductor device p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data ... | 05/10/2011 |
| 7933149 | Non-volatile memory device A non-volatile memory device and a method of fabricating the same are disclosed. The method includes the steps of: providing a semiconductor substrate having isolation layers in an isolation region, a tunnel insulating layer formed between the isolation layers, and ... | 04/26/2011 |
| 7920418 | Nonvolatile memory devices and methods of forming the same A nonvolatile memory device includes a semiconductor substrate of a first conductivity type, a plurality of word lines on the semiconductor substrate, each the plurality of word lines including a floating gate of a second conductivity type. A ground select line and ... | 04/05/2011 |
| 7894257 | Low voltage low cost non-volatile memory Methods, circuits, processes, devices, and/or arrangements for providing a non-volatile memory (NVM) cell are disclosed. In one embodiment, an NVM cell can include: (i) a floating gate in a gate layer, where the floating gate is over an insulating layer, and the ins... | 02/22/2011 |
| 7885106 | Nonvolatile semiconductor memory device and method for driving same A nonvolatile semiconductor memory device includes: a semiconductor substrate including a first channel, and a source region and a drain region provided on both sides of the first channel; a first insulating film provided on the first channel; a charge retention lay... | 02/08/2011 |
| 7876610 | Memory cell array with specific placement of field stoppers A plurality of first transistors formed on a substrate share a gate electrode. Isolation regions isolate the plurality of first transistors from one another. In the region where the plurality of first transistors, an impurity region is formed in such a manner that i... | 01/25/2011 |
| 7821823 | Semiconductor memory device, method of driving the same and method of manufacturing the same Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on ... | 10/26/2010 |
| 7821824 | Semiconductor integrated circuit having buses with different data transfer rates A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory are... | 10/26/2010 |
| 7778072 | Method for fabricating charge-trapping memory A manufacturing method of a charge-trapping memory device is provided. This method includes forming a stacked structure having at least a charge-trapping medium. An annealing process in a hydrogen gas is then performed on the stacked structure subsequent to the devi... | 08/17/2010 |
| 7751236 | MEM suspended gate non-volatile memory A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention. ... | 07/06/2010 |
| 7733694 | Nonvolatile semiconductor memory having a floating gate electrode formed within a trench According to an aspect of the invention, a nonvolatile semiconductor memory comprises: a semiconductor substrate; a trench formed in the semiconductor substrate; a first insulating film being formed on a wall surface of the trench; a floating gate electrode formed o... | 06/08/2010 |
| 7733728 | Non-volatile semiconductor memory device Disclosed is to enable high speed reading from a storage node when a read is executed. A main cell array is constituted from main cell division units 20a. Each main cell division unit 20a includes select gates SG that extend in a vertical... | 06/08/2010 |
| 7663912 | Non-volatile memory device and method of fabricating the same A non-volatile memory device and a method of fabricating the same are disclosed. The method includes the steps of: providing a semiconductor substrate having isolation layers in an isolation region, a tunnel insulating layer formed between the isolation layers, and ... | 02/16/2010 |
| 7652917 | Semiconductor device In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolate... | 01/26/2010 |
| 7623371 | Semiconductor device p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data ... | 11/24/2009 |
| RE40976 | Common source EEPROM and flash memory A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated w... | 11/17/2009 |
| 7613041 | Methods for operating semiconductor device and semiconductor memory device Methods and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductiv... | 11/03/2009 |
| 7580279 | Flash memory cells with reduced distances between cell elements An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching... | 08/25/2009 |
| 7573738 | Mode selection in a flash memory device A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the segment mode causes the device to output selected memory segments. Selec... | 08/11/2009 |
| 7567448 | Content addressable memory cell having a single floating gate transistor A method and system for providing a content addressable memory cell (CAM) as well as the CAM are disclosed. In one aspect, the method and system include providing a plurality of memory cells, at least one search line and at least one match line. Each of the CAM cell... | 07/28/2009 |
| 7554841 | Circuit for storing information in an integrated circuit and method therefor A circuit has a storing portion, a write portion and a read portion. In one embodiment, read portion has a transistor which has a substantially thinner gate oxide than the transistors in the storing portion and the transistors in the write portion. In an alternate e... | 06/30/2009 |