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| Number | Title | Issue Date |
| 7443729 | System that compensates for coupling based on sensing a neighbor using coupling Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing ele... | 10/28/2008 |
| 7337282 | Memory system and process for controlling a memory component to achieve different kinds of memory characteristics on one and the same memory component According to the invention, a memory system, and a process for controlling a memory component, to achieve different kinds of memory characteristics on one and the same memory component, is provided, the process comprising the steps: | 02/26/2008 |
| 7292465 | Ferroelectric random access memory device, display drive integrated circuit, and electronic apparatus A ferroelectric random access memory device, includes at least one bit line extending in a first direction; a plurality of first active regions, arranged in the first direction a predetermined distance from each other on one side of the bit line, each being connecte... | 11/06/2007 |
| 7286414 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controll... | 10/23/2007 |
| 7268809 | Analog buffer memory for high-speed digital image capture A digital imaging system uses a high density, high speed analog/multi-level memory to temporarily store image data at high rates for extended periods of time. A portion of the stored data is transmitted for image processing and compression. When image processing and... | 09/11/2007 |
| 7243165 | Parallel pattern detection engine A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern ha... | 07/10/2007 |
| 7075825 | Electrically alterable non-volatile memory with n-bits per cell An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell can be performed without actually reading the memory state of the cell during the programming operation. A plurality of th... | 07/11/2006 |
| 7068542 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controll... | 06/27/2006 |
| 7064453 | Semiconductor memory device including a gate electrode with a recess A configuration is provided to reduce variations in the width of the gate of a read-out transistor without increasing the surface area of a memory cell. To do this, a recess is provided in an inner corner of a gate electrode that is bent into an L-shape. The recess ... | 06/20/2006 |
| 7053945 | Image sensor having boosted reset A power supply reset boosting element which boosts a level of the reset voltage to a level higher than the level of the power supply. The boosted voltage is isolated from both the power supply and from undesired switching by special transistors which can withstand t... | 05/30/2006 |
| 7006384 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controll... | 02/28/2006 |
| 7002872 | Semiconductor memory device with a decoupling capacitor A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge stori... | 02/21/2006 |
| 6949402 | Method of forming a non-volatile resistance variable device A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcoge... | 09/27/2005 |
| 6906354 | T-RAM cell having a buried vertical thyristor and a pseudo-TFT transfer gate and method for fabricating the same A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual devices. Each T-RAM cell is planar and has a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate. The buried vertical thyristor is located beneath t... | 06/14/2005 |
| 6807604 | Method of refreshing a dynamic memory A method of refreshing a dynamic memory intended for storing variables involved in operations performed by a processor, includes a step of planning 10 in the course of which an order and a timing of the operations are established, a step of estimating 13 | 10/19/2004 |
| 6759721 | Integrated semiconductor DRAM-type memory device and corresponding fabrication process An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two pote... | 07/06/2004 |
| 6426238 | Charge transfer device and solid image pickup apparatus using the same A charge transfer device is provided, capable of preventing degradation of the charge transfer efficiency when the channel width becomes narrower due to the narrow channel effect. The charge transfer device of the present invention is obtained by forming ... | 07/30/2002 |
| 6319668 | Method for tagging and screening molecules Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and... | 11/20/2001 |
| 6212095 | Integrated circuit charge coupling circuit A charge pump coupling circuit is described for more efficiently coupling a final capacitive stage of a charge pump to a capacitive load. The coupling circuit is has primarily resistive characteristics to allow for a greater load voltage. The resistive co... | 04/03/2001 |
| 6181630 | Method of stabilizing data stored in volatile memory A system for preventing data loss when volatile memory is used to store data either internal or external to a host computer. In the preferred embodiment, the system provides uninterrupted power to the volatile memory and to a non-volatile storage device s... | 01/30/2001 |
| 6040992 | Integrated circuit charge coupling circuit A charge pump coupling circuit is described for more efficiently coupling a final capacitive stage of a charge pump to a capacitive load. The coupling circuit is has primarily resistive characteristics to allow for a greater load voltage. The resistive co... | 03/21/2000 |
| 6036834 | Process and devices for the electrolytic formation of a deposit on a chosen group of electrodes A method and device for the electrolytic formation of a deposit on a group of electrodes of an electrolysis support. The support has a plurality of electrodes. Electric charges are selectively deposited on chosen electrodes. The support is placed in the p... | 03/14/2000 |
| 5949708 | Integrated circuit charge coupling circuit A charge pump coupling circuit is described for more efficiently coupling a final capacitive stage of a charge pump to a capacitive load. The coupling circuit is has primarily resistive characteristics to allow for a greater load voltage. The resistive co... | 09/07/1999 |
| 5625583 | Analog memory system having an integrated circuit frequency domain processor An optical system has an optical image projected on an analog memory, such as a CCD array, generating analog charge signals in the analog memory. The analog charge signals are processed with an analog to digital converter to generate digital information. ... | 04/29/1997 |
| 5610580 | Motion detection imaging device and method A motion detection and imaging method and device 10 for carrying out the method are provided. The device 10 comprises a housing 12 containing a CCD 18 for providing digital image data, a lens 16 for focusing an image on the CCD 18 and a solid state non-vo... | 03/11/1997 |
| 5485597 | A CCD array memory device achieving high speed accessing by writing and reading data through a cache memory A memory device for storing analog or multilevel data which is easy to produce and of a small scale. The memory device according to the present invention circulates data between a plurality of linear CCD arrays which store data as electrical charges, allo... | 01/16/1996 |
| 5420812 | Bidirectional type CCD A bidirectional-type charge coupled device in which the directions of the signal flow can be changed by an external controlling signal.... | 05/30/1995 |
| 5386384 | Parallel CCD memory chip and method of matching therewith A fully parallel CCD memory chip of N address lines which detects in just one clock cycle, a perfect match between an input pattern and any of a plurality of stored patterns and also detects in less than (N+1)-comparison cycles and still just one XOR oper... | 01/31/1995 |
| 5379252 | Memory device The present invention provides a memory device for realizing an analog memory that or a multilevel memory easy to produce and requires only small scale circuitry. The memory device comprises: a CCD array "Ai" linearly arranged a refresh circuit "R" connec... | 01/03/1995 |
| 5373464 | CCD array memory device having dual, independent clocks of differing speeds The present invention provides a memory device for preventing data circulating on a plural number of linear CCD array from being corrupted, for accessing data at a high speed, and for reducing the device's electric power consumption. A memory device accor... | 12/13/1994 |
| 5339275 | Analog memory system An improved analog memory arrangement is interfaced to receive digital signals through a digital to analog converter and is interfaced to output analog signals through an analog to digital converter. Analog refreshing is implemented to reduce degradation ... | 08/16/1994 |
| 5289408 | Memory apparatus using tunnel current techniques A scanning tunneling microscope memory apparatus comprises first and second integrated circuit (IC) substrates. First and second cantilevers, which can be moved by piezoelectric elements, are arranged on the first and second IC substrates, respectively. T... | 02/22/1994 |
| 5168463 | Shift register apparatus for storing data therein An apparatus for storing digital data includes a clock pulse source and plural serial shift register stages storing data bits. Digital data signals, each having plural databits, are coupled to and shifted in the stages in synchronization with the clock pu... | 12/01/1992 |
| 5111436 | 2D charge coupled device memory with acoustic charge transport multiplexer Two dimensional charge coupled device (CCD) memories are coupled to acoustic charge transport devices (ACT) which act as input and/or output multiplexers for the memories. In a preferred embodiment of the invention, the input to a NXM memory is in the for... | 05/05/1992 |
| 5077762 | Charge transfer device having MIM structures and method for driving the same There is provided a one-dimensional MIM array having MIM structures arranged on an insulative substrate in a lateral direction and each used as a unit for storing a signal charge, for sequentially storing and transferring the signal charges between the ad... | 12/31/1991 |
| 5030953 | Charge domain block matching processor A full search block matching algorithm includes a charge-domain serial tapped delay line as an input buffer, and an array of charge domain signal processors. The delay line shifts and holds analog sampled data which are in the form of charge packets. At e... | 07/09/1991 |
| 5018172 | Charge-coupled SPS memory device In a charge-coupled SPS memory device, in which the transport takes place according to the "pushing" principle, it may occur that during the SP transport charge is injected into the substrate and diffuses via the substrate into the memory mat. In order to... | 05/21/1991 |
| 4992982 | SPS type charge coupled device memory suitable for processing video information with increased speed An SPS charge coupled device memory is described which is useful for storing video pictures. The memory avoids accumulation of charge below the de-interlacing electrodes controlling the transfer of data to the series output register by using two different... | 02/12/1991 |
| 4987558 | Semiconductor memory with voltage stabilization In dynamic memories, generally a fluctuation of 10% of the nominal value of the supply voltage is allowed. Since, when reading, the input gate is applied to the supply, this fluctuation in the supply results in 20% of fluctuation in the charge packet form... | 01/22/1991 |
| 4951302 | Charge-coupled device shift register A two phase shift register comprises four serial registers each having an input section, a transfer section, and a lead-in section disposed between the input section and the transfer section. The input sections provide respective sequences of charge sampl... | 08/21/1990 |
