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| Number | Title | Issue Date |
| 8094491 | Semiconductor device A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal th... | 01/10/2012 |
| 7969777 | Thyristor-based memory array having lines with standby voltages A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in se... | 06/28/2011 |
| 7940560 | Memory cells, memory devices and integrated circuits incorporating the same A memory device is provided which includes a write bit line, a read bit line, and at least one memory cell. The memory cell includes a write access transistor, a read access transistor coupled to the read bit line and to the first write access transistor, and a gate... | 05/10/2011 |
| 7894256 | Thyristor based memory cell A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has tw... | 02/22/2011 |
| 7764540 | Semiconductor memory device By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing f... | 07/27/2010 |
| 7755937 | Semiconductor device A semiconductor device, includes a memory cell including a thyristor element with a gate having a pnpn structure formed on a semiconductor substrate and having first and second terminals, and an access transistor formed on the semiconductor substrate and having firs... | 07/13/2010 |
| 7692960 | Scheme of semiconductor memory and method for operating same A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the ... | 04/06/2010 |
| 7630235 | Memory cells, memory devices and integrated circuits incorporating the same A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transisto... | 12/08/2009 |
| 7619917 | Memory cell with trigger element A memory device includes a plurality of word lines extending as rows and bit lines extending as columns. A memory cell is coupled between a word line and a bit line, wherein the memory cell includes a unipolar memory element selectively coupled to the bit line via a... | 11/17/2009 |
| 7486553 | Nonvolatile storage device and method of manufacturing the same, and storage device and method of manufacturing the same A nonvolatile storage device includes a plurality of bit lines 21 arranged in a column direction on a substrate; a plurality of word lines 35 arranged in a row direction on the substrate; a memory cell array 20 having a plurality of memory cells... | 02/03/2009 |
| 7460395 | Thyristor-based semiconductor memory and memory array with data refresh A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in se... | 12/02/2008 |
| 7397696 | Current sensing architecture for high bitline voltage, rail to rail output swing and Vcc noise cancellation The present invention pertains to a circuit arrangement that, in one example, facilitates reading or determining an amount of current that flows through a memory cell when one or more voltages are applied to the cell. The amount of current resulting from the applied... | 07/08/2008 |
| 7376008 | SCR matrix storage device One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column o... | 05/20/2008 |
| 7336523 | Memory device using nanotube cells A memory device using a nanotube cell comprises a plurality of nanotube sub-cell arrays each having a hierarchical bit line structure including a main bit line and a sub-bit line. In the memory device, a nanotube cell array comprising a capacitor and a PNPN nanotube... | 02/26/2008 |
| 7304327 | Thyristor circuit and approach for temperature stability Switching operations, such as those used in memory devices, are enhanced using a semiconductor device having a thyristor adapted to switch between conducting and blocking states and operate at low power. According to an example embodiment of the present invention, t... | 12/04/2007 |
| 7289351 | Method of programming a resistive memory device In an embodiment of a method of programming a resistive memory device, an electrical potential is applied to the gate of a transistor operatively associated with the resistive memory device, and successive, increasing electrical potentials are applied across the res... | 10/30/2007 |
| 7289358 | MTP NVM elements by-passed for programming Non-Volatile Memory (NVM) cells include a selection circuit for providing an output based on selecting between an input data signal and an output of a Multiple Time Programmable (MTP) NVM element. The input data signal may be latched by a latch circuit such as a fli... | 10/30/2007 |
| 7184312 | One transistor SOI non-volatile random access memory cell One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transisto... | 02/27/2007 |
| 7151029 | Memory device and method of making the same A multi-stable memory or data storage element is used in crosspoint data-storage arrays, as a switch, a memory device, or as a logical device. The general structure of the multi-stable element comprises a layered, composite medium that both transports and stores cha... | 12/19/2006 |
| 7130216 | One-device non-volatile random access memory cell One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between... | 10/31/2006 |
| 7109539 | Multiple-bit magnetic random access memory cell employing adiabatic switching A multiple-bit memory cell for use in a magnetic random access memory circuit includes a first adiabatic switching storage element having a first anisotropy axis associated therewith and a second adiabatic switching storage element having a second anisotropy axis as... | 09/19/2006 |
| 7095643 | Re-writable memory with multiple memory layers A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminal... | 08/22/2006 |
| 7078739 | Thyristor-based memory and its method of operation A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of... | 07/18/2006 |
| 7054191 | Method and system for writing data to memory cells A first and a second set of memory cells are connected to the same first word line and second word line. At the commencement of data writing, the first word line is set up. The first set of memory cells is read and temporarily stored into a buffer. At about the same... | 05/30/2006 |
| 7042027 | Gated lateral thyristor-based random access memory cell (GLTRAM) One aspect of the present subject matter relates to a memory cell, or more specifically, to a scalable GLTRAM cell that provides DRAM-like density and SRAM-like performance. According to various embodiments, the memory cell includes an access transistor and a gated,... | 05/09/2006 |
| 6967358 | Thyristor-type memory device A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word ... | 11/22/2005 |
| 6961262 | Memory cell isolation Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method in... | 11/01/2005 |
| 6944051 | Data restore in thryistor based memory devices In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, ... | 09/13/2005 |
| 6937502 | Re-recordable data storage medium utilizing conduction barrier A re-recordable data storage medium is disclosed. The medium in one embodiment includes a phase-changeable layer and an intermediate layer. A junction between the intermediate layer and another layer of the medium provides a conduction barrier under no illumination ... | 08/30/2005 |
| 6917078 | One transistor SOI non-volatile random access memory cell One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transisto... | 07/12/2005 |
| 6906939 | Re-writable memory with multiple memory layers A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminal... | 06/14/2005 |
| 6898115 | Magnetoresistive element, and magnetic memory using the same A magnetoresistive film has at least a first magnetic layer, a second magnetic layer, a nonmagnetic layer, a third magnetic layer, and a fourth magnetic layer stacked in the order named. In the magnetoresistive film, at least the first magnetic layer contains Gd and... | 05/24/2005 |
| 6881623 | Method of forming chalcogenide comprising devices, method of forming a programmable memory cell of memory circuitry, and a chalcogenide comprising device A chalcogenide material is formed to a first thickness over the first conductive electrode material. The chalcogenide material includes AxBy. A layer that includes a metal is formed to a second thickness over the chalcogenide material. The meta... | 04/19/2005 |
| 6845026 | Thyristor-based content addressable memory (CAM) cells A content addressable memory (CAM) cell includes a memory cell storing data values. The memory cell includes a surrounding-gate thyristor and an access transistor. The CAM cell also includes a compare circuit coupled among the memory cell and a match line. The compa... | 01/18/2005 |
| 6756612 | Carrier coupler for thyristor-based semiconductor device Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a ... | 06/29/2004 |
| 6727529 | Semiconductor capacitively-coupled NDR device and related applications in high-density high-speed memories and in power switches A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitiv... | 04/27/2004 |
| 6690038 | Thyristor-based device over substrate surface A semiconductor device having a thyristor is arranged in a manner that reduces or eliminates manufacturing difficulties commonly experienced in the formation of such devices, as well as facilitates the implementation of the semiconductor device in a varie... | 02/10/2004 |
| 6545297 | High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CM... | 04/08/2003 |
| 6448586 | Semiconductor current-switching device having operational enhancer and method therefor A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure wit... | 09/10/2002 |
| 6229161 | Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure wit... | 05/08/2001 |
