Class 365/176 - Silicon on sapphire (SOS)

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter in which the storage element is silicon on
No. of patents: 24
Last issue date: 04/19/2011

Number	Title	Issue Date
7929343	Methods, devices, and systems relating to memory cells having a floating body Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may furth...	04/19/2011
7408811	NAND-type flash memory on an SOI substrate with a carrier discharging operation A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active area...	08/05/2008
7365396	SOI SRAM products with reduced floating body effect A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region o...	04/29/2008
7123509	Floating body cell memory and reading and writing circuit thereof A semiconductor integrated circuit device is provided, which includes a semiconductor layer formed via an embedded insulation film on a substrate and an FBC (Floating Body Cell) which stores data by accumulating a majority carrier in a floating channel body formed o...	10/17/2006
7038282	Semiconductor storage device A semiconductor storage device includes a voltage supply circuit generating a voltage of 5V, a voltage polarity inversion circuit generating a voltage of −5V, a select-and-connect circuit supplying the voltages of 5V and −5V to a memory cell array, a 5 V voltage...	05/02/2006
6990016	Method of making memory cell utilizing negative differential resistance devices A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in ...	01/24/2006
6954235	Silicon-on-sapphire display apparatus and method of fabricating same A liquid crystal display includes: a) a sapphire substrate having a first crystal lattice structure; b) a single crystal silicon structure having a thickness no greater than about 100 nanometers affixed to the sapphire substrate to create a silicon-on-sapphire struc...	10/11/2005
6900503	SRAM formed on SOI substrate An SRAM capable of reducing the overall area consumed by the circuit and capable of improving the mobility and operational characteristics of a PMOS transistor is provided. The SRAM is formed on an SOI substrate having first and second active areas. A first access N...	05/31/2005
6577522	Semiconductor memory device including an SOI substrate A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region ...	06/10/2003
6278287	Isolated well transistor structure for mitigation of single event upsets CMOS circuits are made resistant to erroneous signals produced by the impact of high energy charged particles (commonly known in the literature as Single Event Upset or SEU) by the addition of upset immune transistor structures into the circuits in such a...	08/21/2001
5943258	Memory with storage cells having SOI drive and access transistors with tied floating body connections An integrated circuit (10). The integrated circuit comprises a first SOI transistor (AT3) having a body and for performing first function. The integrated circuit further comprises a second SOI transistor (DT3) having a body and for performing a second fun...	08/24/1999
5383149	Ulsi mask ROM structure and method of manufacture A ROM device provides a double density memory array. The word line array is composed of transversely disposed conductors sandwiched between two arrays of bit lines which are orthogonally disposed relative to the word line array. The two arrays of bit line...	01/17/1995
5299155	Dynamic random access memory device with capacitor between vertically aligned FETs A dynamic random access memory device for storing 2-bit information, including a memory cell having two access transistors and one capacitor, wherein one of the access transistors is composed of a thin film transistor and disposed above the other access t...	03/29/1994
5146299	Ferroelectric thin film material, method of deposition, and devices using same A ferroelectric device that comprises a polarizing thin film of BaMF4 deposited on a substrate. Ba is barium, M is one of the metals of the group consisting of iron (FE), manganese (Mn), cobolt (Co), nickel (Ni), magnesium (Mg), and zinc (Zn). ...	09/08/1992
5032891	Semiconductor memory device and manufacturing method thereof Disclosed is a semiconductor memory device comprising an SOI substrate in which a semiconductor film is formed on a semiconductor substrate with an insulating film interposed therebetween. A memory cell structure is formed by a switching MOS transistor fo...	07/16/1991
4866669	Electronic memory device utilizing silicon-on-sapphire transistors An electronic memory device is disclosed which utilizes silicon-on-sapphire SOS) transistors that exhibit binary states dependent upon the dose of ionizing radiation to which they are subjected. A memory utilizing such SOS transistors may have information ...	09/12/1989
4730275	Circuit for reducing the row select voltage swing in a memory array A circuit reduces the row select voltage swing in a memory array, thereby reducing access time, power dissipation, disturb problems, glitches on the output, and alpha particle sensitivity. A row driver transistor is coupled between a first voltage source ...	03/08/1988
4527181	High density semiconductor memory array and method of making same A semiconductor device according to the present invention including a first semiconductor region formed on an insulating substrate which is a bit line and, another or second semiconductor region formed on the substrate which is a power supply line. The se...	07/02/1985
4368524	Semiconductor device A semiconductor device for comprising electrically alterable read-only memories formed in and on the same silicon substrate is disclosed. The read-only memories are driven by both a first voltage having one polarity and a second voltage having the opposit...	01/11/1983
4253162	Blocked source node field-effect circuitry A unidirectional conducting element is series connected between an input terminal and the source electrode of an insulated-gate field-effect transistor (IGFET) having an electrically floating substrate. The unidirectional conducting element is poled to co...	02/24/1981
4142251	Field programmable read-only-memory A P-channel and an N-channel MOS device share a common floating gate. Avalanche injection of electrons via the P-channel device or avalanche injection of holes via the N-channel device allows the storage of one of two distinct states. Furthermore, the sto...	02/27/1979
4074239	Memory cell with nondestructive recall In a semiconductor memory cell in which binary data is represented by the density of minority carriers stored in the inversion regions of two isolated MIS capacitors, a method of nondestructively recalling the datum stored therein is described. In this me...	02/14/1978
3992703	Memory output circuit A unique memory output integrated circuit disclosed including a memory output driver having an output terminal at which data may be read, a gated power amplifier, and a single ended multiplexer stage which, in the preferred embodiment, is adapted to be in...	11/16/1976
3990056	High speed memory cell An improved very high speed, static random access memory cell disclosed which is comprised of complementary metal oxide semiconductor field effect transistors which may be formed by silicon on sapphire techniques. To maximize the speed of the read operati...	11/02/1976

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Class 365/176 - Silicon on sapphire (SOS)