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| Number | Title | Issue Date |
| 7969776 | Data cells with drivers and methods of making and operating the same Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconduct... | 06/28/2011 |
| 7957206 | Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plura... | 06/07/2011 |
| 7944743 | Methods of making a semiconductor memory device One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic â... | 05/17/2011 |
| 7894255 | Thyristor based memory cell A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolati... | 02/22/2011 |
| 7859897 | Semiconductor memory device and driving method thereof A memory includes: memory cells including floating bodies, wherein in a data holding state, a potential of the first gate electrode is set to be higher than one of potentials of the source and drain layer and lower than the other of the potentials of the source and ... | 12/28/2010 |
| 7817466 | Semiconductor array including a matrix of cells and a method of making a semiconductor array having a matrix of cells A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control li... | 10/19/2010 |
| 7787293 | Semiconductor memory device This disclosure concerns a semiconductor memory device including Fin semiconductors extending in a first direction; source layers provided in the Fin semiconductors; drain layers provided in the Fin semiconductors; floating bodies provided in the Fin semiconductors ... | 08/31/2010 |
| 7787292 | Carbon nanotube fuse element In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programm... | 08/31/2010 |
| 7729149 | Content addressable memory cell including a junction field effect transistor A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. T... | 06/01/2010 |
| 7688624 | Semiconductor device It is an object of the present invention to provide a volatile organic memory in which data can be written other than during manufacturing and falsification by rewriting can be prevented, and to provide a semiconductor device including such an organic memory. It is ... | 03/30/2010 |
| 7589995 | One-transistor memory cell with bias gate One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic â... | 09/15/2009 |
| 7529125 | Semiconductor device and operating method thereof An object is to provide a semiconductor device capable of reducing an area of the semiconductor device, reading data reliably, and simplifying replacement of data. A memory cell and a data line are controlled with a reset signal, so that data can be reliably outputt... | 05/05/2009 |
| 7471558 | Semiconductor storage device A semiconductor storage device comprising: unit blocks each including memory cells, first row of sense amplifiers on one side of bit lines; second row of sense amplifiers on an other side of the bit lines; first switch means which switches a connection state between... | 12/30/2008 |
| 7443741 | DQS strobe centering (data eye training) method A method for calibrating a data valid window including the steps of: (A) setting a base delay of one or more datapaths to a predetermined value, (B) determining an optimum offset delay value for each of the one or more datapaths based upon actual memory accesses and... | 10/28/2008 |
| 7414883 | Programming a normally single phase chalcogenide material for use as a memory or FPLA A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by ... | 08/19/2008 |
| 7405963 | Dynamic data restore in thyristor-based memory device A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the... | 07/29/2008 |
| 7405967 | Microelectronic programmable device and methods of forming and programming the same A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applyin... | 07/29/2008 |
| 7382650 | Method and apparatus for sector erase operation in a flash memory array A memory device is provided which includes a substrate, a common P-well isolated from the substrate, a plurality of sectors, and a common sector selection transistor configured to select one of the sectors for erasure. Each of the sectors share the same common secto... | 06/03/2008 |
| 7379315 | Apparatus and methods for optically-coupled memory systems Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module ... | 05/27/2008 |
| 7372065 | Programmable metallization cell structures including an oxide electrolyte, devices including the structure and method of forming same A microelectronic programmable structure suitable for storing information, a device including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrod... | 05/13/2008 |
| 7369424 | Programmable memory cell and operation method A memory array including a plurality of programmable memory cells, a plurality of column lines and a plurality of row lines is introduced. Each of the programmable memory cells is coupled to corresponding one of the column lines and corresponding one of the row line... | 05/06/2008 |
| 7367119 | Method for forming a reinforced tip for a probe storage device Systems and methods in accordance with the present invention can include a tip contactable with a media. In an embodiment, the tip comprises a substantially hollow structure formed of a metal. The tip can be formed by depositing a first metal layer over silicon ther... | 05/06/2008 |
| 7362605 | Nanoelectromechanical memory cells and data storage devices Nanoelectromechanical (NEM) memory cells are provided by anchoring a conductive nanometer-scale beam (e.g., a nanotube) to a base and allowing a portion of the beam to move. A charge containment layer is provided in the vicinity of this free-moving portion. To read ... | 04/22/2008 |
| 7360005 | Software programmable multiple function integrated circuit module An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable func... | 04/15/2008 |
| 7359238 | Semiconductor nonvolatile storage circuit A semiconductor nonvolatile storage circuit capable of stably storing and holding information by preventing pseudo-writing in storing/holding FETs is realized. The semiconductor nonvolatile circuit includes a first FET MNM1 forming a source-drain path between... | 04/15/2008 |
| 7352603 | Apparatus and methods for optically-coupled memory systems Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module ... | 04/01/2008 |
| 7352649 | High speed array pipeline architecture A memory device including a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output l... | 04/01/2008 |
| 7349266 | Memory device with a data hold latch A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line ... | 03/25/2008 |
| 7349273 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 03/25/2008 |
| 7335580 | Lamellar-derived microelectronic component array and method of fabrication Sub-lithographic lamella and pillar structures defined by larger lines or lamellae are described. A static random access memory (SRAM) cell structure is created in a three-dimensional format as a vertical stack of wired transistors. These transistors are fabricated ... | 02/26/2008 |
| 7336524 | Atomic probes and media for high density data storage A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact probe can include a silicon core having a conductive coating. Contact pro... | 02/26/2008 |
| 7335395 | Methods of using pre-formed nanotubes to make carbon nanotube films, layers, fabrics, ribbons, elements and articles Methods of Using Preformed Nanotubes to Make Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles are disclosed. To make various articles, certain embodiments provide a substrate. Preformed nanotubes are applied to a surface of the substrate to cre... | 02/26/2008 |
| 7332950 | DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d... | 02/19/2008 |
| 7324373 | Semiconductor device and short circuit detecting method A short circuit detection region includes an insulating film, plural first conductor traces and plural second conductor traces which are embedded in the insulating film with only their surfaces being exposed, and the first conductor trace is constructed by integrall... | 01/29/2008 |
| 7324367 | Memory cell and method for forming the same A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the su... | 01/29/2008 |
| 7321505 | Nonvolatile memory utilizing asymmetric characteristics of hot-carrier effect A memory circuit includes a latch having a first node and a second node, a first MIS transistor having source/drain nodes thereof coupled to the first node and to a plate line, respectively, and a gate node thereof coupled to a word selecting line, a second MIS tran... | 01/22/2008 |
| 7310260 | High performance register accesses The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the cpu/mpu does not require any acknowledge or wait signal from the regi... | 12/18/2007 |
| 7310266 | Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing inform... | 12/18/2007 |
| 7309630 | Method for forming patterned media for a high density data storage device Systems in accordance with the present invention can include a tip contactable with a media, the media including a substrate and a plurality of cells disposed over the substrate, one or more of the cells being electrically isolated from the other of the cells by a m... | 12/18/2007 |
| 7310259 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 12/18/2007 |
