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| Number | Title | Issue Date |
| 7881088 | Content addressable memory device The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (c... | 02/01/2011 |
| 7859878 | Design structure for implementing matrix-based search capability in content addressable memory devices A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare c... | 12/28/2010 |
| 7848128 | Apparatus and method for implementing matrix-based search capability in content addressable memory devices A content addressable memory (CAM) device includes an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row a... | 12/07/2010 |
| 7609546 | Multivalue memory storage with two gating transistors Digital memory devices and systems, as well as methods of operating digital memory devices, that include a multivalue memory cell with a first and a second gating transistor arranged in parallel, having a first and a second node, respectively, coupled to a storage e... | 10/27/2009 |
| 7505296 | Ternary content addressable memory with block encoding The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (c... | 03/17/2009 |
| 7417881 | Low power content addressable memory A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled ... | 08/26/2008 |
| 7372741 | Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile memory having circuitry which performs an erase operation and an erase verify operation when the processor specifies the erase operation mode to the nonvolatile memory A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation i... | 05/13/2008 |
| 7349230 | Associative memory cells configured to selectively produce binary or ternary content-addressable memory lookup results Associative memory bit cells are disclosed for selectively producing binary or ternary content-addressable memory lookup results. Associative memory bit cells are grouped together to act as n binary content-addressable memory cells (CAM) bits or m ternary content-ad... | 03/25/2008 |
| RE40075 | Method of multi-level storage in DRAM and apparatus thereof A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference... | 02/19/2008 |
| 7319606 | Memory A memory capable of effectively reducing the chip size not only by sharing a read/write circuit but also by reducing a memory cell size is provided. This memory comprises a first memory cell array having a plurality of first memory cells, a second memory cell array ... | 01/15/2008 |
| 7301813 | Compensating for coupling during read operations of non-volatile memory Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing ele... | 11/27/2007 |
| 7286414 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controll... | 10/23/2007 |
| 7274580 | Content addressable memory device A ternary content addressable memory (TCAM) device comprising a plurality of TCAM cells for storing data, each TCAM cell having two memory cells and a comparison circuit for comparing between data stored in the memory cells and data input on a search line pair conne... | 09/25/2007 |
| 7275140 | Flash memory management method that is resistant to data corruption by power loss The present invention includes a method of managing page-based data storage media such as flash media, a system that uses the method, and a computer-readable storage medium bearing code for implementing the method. For each page, a corresponding risk zone, of other ... | 09/25/2007 |
| 7268573 | Apparatus for generating test stimulus signal having current regardless of internal impedance changes of device under test An apparatus for generating a current source test stimulus signal having a constant current regardless of an internal impedance value of a device under test includes a voltage source generation unit and a voltage to current (V/I) converter. The voltage source genera... | 09/11/2007 |
| 7259980 | Memory A memory capable of effectively reducing the chip size not only by sharing a read/write circuit but also by reducing a memory cell size is provided. This memory comprises a first memory cell array having a plurality of first memory cells, a second memory cell array ... | 08/21/2007 |
| 7259979 | Area efficient stacked TCAM cell for fully parallel search An area efficient stacked TCAM cell for fully parallel search. The TCAM cell includes a top half circuit portion interconnected with a replicated bottom half circuit portion such that there is a shared match line between each of the half circuit portions. Each TCAM ... | 08/21/2007 |
| 7246268 | Method and apparatus for dynamic degradation detection Methods and apparatus for automatically detecting when a memory system has significantly degraded are disclosed. According to one aspect of the present invention, a method for determining a status associated with a memory system which includes a plurality of sectors... | 07/17/2007 |
| 7239546 | Semiconductor device with a nonvolatile semiconductor memory circuit and a plurality of IO blocks Only by replacing a conventional fuse element used for a redundant repair of a memory with a CMOS device, since physical processing is not required, there is an advantage on a circuit area in which the upper interconnection can be utilized. However, on a design of a... | 07/03/2007 |
| 7230840 | Content addressable memory with configurable class-based storage partition A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circ... | 06/12/2007 |
| 7221586 | Memory utilizing oxide nanolaminates Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region b... | 05/22/2007 |
| 7221017 | Memory utilizing oxide-conductor nanolaminates Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A float... | 05/22/2007 |
| 7221595 | Semiconductor device and method of generating sense signal A semiconductor device includes a first cascode circuit having a first current mirror amplifying a reference current flowing through a data line of a reference cell, and a second current mirror generating a first potential from an amplified reference current; and a ... | 05/22/2007 |
| 7219294 | Early CRC delivery for partial frame Memory apparatus and methods transmit and receive a CRC code for a first portion of a frame before the second portion of the frame is finished being transferred. The CRC may be used to check the first portion of the frame before the second portion of the frame is co... | 05/15/2007 |
| 7219207 | Reconfigurable trace cache According to one embodiment a computer system is disclosed. The computer system includes a microprocessor and a chipset coupled to the microprocessor. The microprocessor removes stale branch instructions prior to the execution of a first cache line by finding existi... | 05/15/2007 |
| 7206876 | Input/output interface of an integrated circuit device An integrated circuit includes M first terminals and N second terminals, where M and N are positive integers, and where M>N>1. The circuit further includes a converter which receives M base-A-level input signals from the M first terminals, respectively, encodes each... | 04/17/2007 |
| 7193893 | Write once read only memory employing floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 03/20/2007 |
| 7184341 | Method of data flow control for a high speed memory A new method of increasing access cycle time in a memory device is achieved. The memory device has three operating states of standby, read, and write. The data lines in the memory device may be pre-charged. The method comprises, first, during the standby state, the ... | 02/27/2007 |
| 7180814 | Low power circuits with small voltage swing transmission, voltage regeneration and wide bandwidth architecture An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven ... | 02/20/2007 |
| 7174419 | Content addressable memory device with source-selecting data translator A method of operation within a content addressable memory (CAM) device. An input data word having a plurality of data bits and a plurality of mask bits is received in the CAM device. An encoded data word is generated based, at least in part, on states of the mask bi... | 02/06/2007 |
| 7170769 | High performance and reduced area architecture for a fully parallel search of a TCAM cell A technique to enhance performance and reduce silicon area for a TCAM system which includes a plurality of CAM blocks that are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of TCAM cells and associated read/... | 01/30/2007 |
| 7166509 | Write once read only memory with large work function floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 01/23/2007 |
| 7154805 | Storage device employing a flash memory A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the ... | 12/26/2006 |
| 7154140 | Write once read only memory with large work function floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 12/26/2006 |
| 7149940 | Device and method for reading data stored in a semiconductor device having multilevel memory cells A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. The multilevel memory cells are arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by n (nā... | 12/12/2006 |
| 7136305 | Sense amplifier with equalizer A sense amplifier is provided that includes a measure branch receiving an input current to be detected, a reference branch receiving a reference current, and an equalizing circuit including a comparator. The equalizing circuit selectively equalizes a measure node of... | 11/14/2006 |
| 7133311 | Low power, high speed read method for a multi-level cell DRAM A method of storing, sensing and restoring three voltage levels (1.5 bit per cell) of a plurality of memory cells in Dynamic random access memory is disclosed. An asymmetrical sense amplifier, ASA, together with a 2 to 2 multiplex, will be used to detect the voltage... | 11/07/2006 |
| 7123519 | Storage device employing a flash memory A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the ... | 10/17/2006 |
| 7112494 | Write once read only memory employing charge trapping in insulators Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain r... | 09/26/2006 |
| 7110275 | High speed NAND-type content addressable memory (CAM) A CAM block includes a CAM array having a plurality of rows and columns of 4-bit NAND-type CAM cells therein. Each of a plurality of the NAND-type cells includes a respective ladder-type compare circuit having four two-transistor rungs. At least one of the plurality... | 09/19/2006 |
