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| Number | Title | Issue Date |
| 8184475 | Robust local bit select circuitry to overcome timing mismatch An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which... | 05/22/2012 |
| 8164945 | 8T SRAM cell with two single sided ports A dual port SRAM cell includes an auxiliary driver transistor on each data node. The SRAM cell is capable of single sided write to each data node. The auxiliary driver transistors in addressed cells may be biased independently of half-addressed cells. During write a... | 04/24/2012 |
| 8159863 | 6T SRAM cell with single sided write An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may ... | 04/17/2012 |
| 8154912 | Volatile memory elements with soft error upset immunity Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected... | 04/10/2012 |
| 8134862 | Semiconductor memory device and semiconductor device An object is to provide a semiconductor memory device which holds data of an SRAM or a flip-flop circuit and holds data in the SRAM while electric power is not supplied from a reader or electric power is not enough, without changing a battery for driving a power sup... | 03/13/2012 |
| 8134863 | Semiconductor memory device A semiconductor device according to the present invention includes a first memory cell array in which a plurality of first memory cells are arranged as a matrix, data being read from or written to the first memory cells, and a second memory cell array in which a plu... | 03/13/2012 |
| 8125820 | Semiconductor memory device A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which c... | 02/28/2012 |
| 8116121 | Semiconductor device and manufacturing methods with using non-planar type of transistors Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A po... | 02/14/2012 |
| 8040717 | SRAM cell and SRAM device A static random access memory (SRAM) cell includes a first to a fourth semiconductor thin plate that are provided on a substrate and are arranged parallel to each other. On respective semiconductor thin plates, there is formed a first four-terminal double-gate field... | 10/18/2011 |
| 8036023 | Single-event upset immune static random access memory cell circuit A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets... | 10/11/2011 |
| 8000131 | Non-volatile field programmable gate array A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complement... | 08/16/2011 |
| 7990760 | Semiconductor SRAM with alternatively arranged P-well and N-well regions A semiconductor memory device comprises a cell array having a plurality of SRAM cells arranged in a bit line direction and a word line direction orthogonal to said bit line direction in a matrix; and a peripheral circuit arranged adjacent to the cell array in the bi... | 08/02/2011 |
| 7990759 | Hardened memory cell The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second... | 08/02/2011 |
| 7986547 | Semiconductor memory device A semiconductor memory device includes a memory cell array having a plurality of read word lines, a plurality of first and second read bit lines, and a plurality of memory cells arranged in array. The memory cell includes a first and a second cell node in complement... | 07/26/2011 |
| 7978503 | Static semiconductor memory with a dummy call and a write assist operation A dummy memory cell for detection of write completion timing is provided as a replica of a memory cell. When assisting a write operation by power supply control and substrate potential control of the memory cell, the timing of ending the write assist operation is de... | 07/12/2011 |
| 7978504 | Floating gate device with graphite floating gate One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon a... | 07/12/2011 |
| 7965541 | Non-volatile single-event upset tolerant latch circuit A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the ... | 06/21/2011 |
| 7965540 | Structure and method for improving storage latch susceptibility to single event upsets A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical co... | 06/21/2011 |
| 7952913 | Back gated SRAM cell One method for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The method includes applying a ground to the back gate of the pair of cross coupled p-type ... | 05/31/2011 |
| 7944735 | Method of making a nanotube-based shadow random access memory Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable ... | 05/17/2011 |
| 7929333 | Semiconductor memory device A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit li... | 04/19/2011 |
| 7924588 | Content addressable memory with concurrent two-dimensional search capability in both row and column directions A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match res... | 04/12/2011 |
| 7924606 | Memory controller and decoder A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectivel... | 04/12/2011 |
| 7920411 | Converting SRAM cells to ROM cells A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged... | 04/05/2011 |
| 7916519 | Burn-in methods for static random access memories and chips A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The... | 03/29/2011 |
| 7907439 | Semiconductor memory device A semiconductor memory device comprises a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing the word lines, and memory cells connected at intersections of the word lines and bit lines, the cell arrays a... | 03/15/2011 |
| 7876602 | Single-event upset immune static random access memory cell circuit, system, and method A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets... | 01/25/2011 |
| 7826253 | Semiconductor memory device and driving method thereof In a reading operation, an off time and a reading time of a holding control transistor is controlled by a replica circuit, so that a read margin is enlarged. Furthermore, a high power source potential and a low power source potential of an SRAM memory cell are switc... | 11/02/2010 |
| 7821817 | Semiconductor storage device In a semiconductor storage device including a transistor for reading port, undesired voltage decrease may occur in a bit line in a reading operation due to a leak current from the transistor for reading port of a memory cell, which may cause a reading error. A semic... | 10/26/2010 |
| 7808812 | Robust 8T SRAM cell This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NM... | 10/05/2010 |
| 7791928 | Design structure, structure and method of using asymmetric junction engineered SRAM pass gates A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The method includes applying a voltage through asymmetric pull-down nFETs with high junction leakage from their body ... | 09/07/2010 |
| 7768820 | Feedback structure for an SRAM cell Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the feedback structure is for use with an integrated circuit and includes... | 08/03/2010 |
| 7733690 | Semiconductor integrated circuit having a latch circuit A semiconductor integrated circuit comprising a data holding circuit sets the data holding circuit to a desired data state by first setting the power-supply voltage of the data holding circuit to be less than a specified voltage, and then setting the power-supply vo... | 06/08/2010 |
| 7719880 | Method and system for semiconductor memory Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portio... | 05/18/2010 |
| 7710765 | Back gated SRAM cell Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during... | 05/04/2010 |
| 7710764 | Semiconductor memory cells with shared p-type well A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit includes: a plurality of memory mats; a local bus... | 05/04/2010 |
| 7706174 | Static random access memory A static random access memory (“SRAM”) comprising: a pair of inverters each having an input and an output; a cross-coupling path coupling the input of a first inverter to the output of a second inverter; and a transmission gate, wherein the transmission gate com... | 04/27/2010 |
| 7626855 | Semiconductor memory device Obtained is a highly-reliable non-volatile memory without increasing the area of a memory cell or adding a step to a CMOS process. The non-volatile memory includes an SRAM cell configured of 6 MOS transistors, a first word line electrically connected to the gate of ... | 12/01/2009 |
| 7619916 | 8-T SRAM cell circuit, system and method for low leakage current An SRAM cell has reduced gate and sub-threshold leakage currents. The SRAM cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored in the SRAM cell. The transistors lower the effective supply voltage a... | 11/17/2009 |
| 7570509 | Semiconductor device, logic circuit and electronic equipment A semiconductor device comprises: a) a multiple layered substrate including a semiconductor substrate, an insulation film formed on the semiconductor substrate, and a semiconductor film, b) a first inverter having a first n-channel type MISFET and a first p-channel ... | 08/04/2009 |
