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| Number | Title | Issue Date |
| 7443715 | SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide the SRAM cell with a definitive asymmetry so that the cell always start... | 10/28/2008 |
| 7443717 | Semiconductor device A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high... | 10/28/2008 |
| 7382678 | Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized de... | 06/03/2008 |
| 7362606 | Asymmetrical memory cells and memories using the cells Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selecti... | 04/22/2008 |
| 7352645 | Memory device A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated w... | 04/01/2008 |
| 7313012 | Back-gate controlled asymmetrical memory cell and memory using the cell Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line s... | 12/25/2007 |
| 7295458 | Eight transistor SRAM cell with improved stability requiring only one word line An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs ... | 11/13/2007 |
| 7254203 | Method and apparatus for use of high sampling frequency A/D converters for low frequency sampling A method and apparatus for adding fill-in clock pulses to an analog to digital converters input clock signal between requests for analog data acquisition. The circuit that provides the fill-in clock pulses is able to detect a request for analog data acquisition, syn... | 08/07/2007 |
| 7242607 | Diode-based memory including floating-plate capacitor and its applications Floating plate memory includes a diode as an access device, wherein the diode has four terminals, the first terminal serves as a word line, the second terminal serves as a storage node, the third terminal is floating, and the fourth terminal serves as a bit line; a ... | 07/10/2007 |
| 7139190 | Single event upset tolerant memory cell layout Half cells of single-event-upset-tolerant memory cells are offset by at least two rows in a memory array. Offsetting the half cells separates them to avoid simultaneous damage to both half cells from a high-energy particle that could otherwise alter multiple nodes a... | 11/21/2006 |
| 7098833 | Tri-value decoder circuit and method A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid... | 08/29/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7018069 | Multi-purpose light A multi-purpose light is disclosed. The multi-purpose light includes a housing, an illumination mechanism provided in the housing for illuminating the mailbox interior and a switch provided on the housing for reversibly activating the illumination mechanism. Aa pivo... | 03/28/2006 |
| 7002856 | Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit... | 02/21/2006 |
| 6970391 | Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit... | 11/29/2005 |
| 6963499 | Static RAM with flash-clear function A memory cell comprises a first and a second inverters connected in a latch configuration. The inverters have respective first and second means for receiving a first and a second voltage supplies, respectively. The cell also comprises means, responsive to a memory c... | 11/08/2005 |
| 6914804 | Memory cells enhanced for resistance to single event upset Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity mo... | 07/05/2005 |
| 6859387 | Three-state binary adders and methods of operating the same Three-state binary adders are disclosed for use in pipelined analog-to-digital converters. According to one advantageous embodiment, a three-state binary adder is provided for use in a digital signal processing system. The three-state binary adder is operable to gen... | 02/22/2005 |
| 6735110 | Memory cells enhanced for resistance to single event upset Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity mo... | 05/11/2004 |
| 6618283 | System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled through a clock tree, and a feedback signal is generated tha... | 09/09/2003 |
| 6529401 | Semiconductor memory A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter includes a NMOS transistor and a PMOS transistor, and an inverter includes a NMOS transistor and a... | 03/04/2003 |
| 6271568 | Voltage controlled resistance modulation for single event upset immunity An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two transistors are pass transistors. The inverters are cross-cou... | 08/07/2001 |
| 6096496 | Supports incorporating vertical cavity emitting lasers and tracking apparatus for use in combinatorial synthesis A combinatorial chemistry bead that includes an electromagnetic spectral emitter that radiates a distinct electromagnetic code for each bead that uniquely identifies each bead, a terminal apparatus for receiving the electromagnetic code from each bead, an... | 08/01/2000 |
| 6088259 | SRAM cell using two single transistor inverters A SRAM cell is disclosed. The SRAM cell comprises: a first inverter having an input and an output; a second inverter having an input and an output, the output of the second inverter capacitively coupled to the input of the first inverter, the input of the... | 07/11/2000 |
| 5966324 | Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells Memory cells which are adjacent to each other along a column direction share a bipolar transistor driving the potential level of a corresponding bit line. Other memory cells which are adjacent to each other in the column direction share another bipolar tr... | 10/12/1999 |
| 5661681 | Semiconductor memory and method of writing, reading, and sustaining data thereof A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emi... | 08/26/1997 |
| 5383153 | Semiconductor memory device with flash-clear function A semiconductor memory device equipped with a flash-clear function has a plurality of flip-flop type memory cells each of which is formed by a first multi-emitter transistor and a second multi-emitter transistor, a clear line and a switching circuit. Each... | 01/17/1995 |
| 5289409 | Bipolar transistor memory cell and method Bipolar transistor memory cell and method for use in a random access memory. A pair of state elements are cross coupled so that they assume opposite states in accordance with signals applied thereto, a pair of bipolar pass transistors are connected to res... | 02/22/1994 |
| 5276638 | Bipolar memory cell with isolated PNP load A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is connected to one of the storage transistors. A base, common to... | 01/04/1994 |
| 5216630 | Static semiconductor memory device using bipolar transistor Disclosed is a bipolar SRAM including, in each memory cell, two NPN multiemitter transistors, with a base of one transistor being cross-connected to a collector of the other transistor. The respective collectors of these two multiemitter transistors in an... | 06/01/1993 |
| 5200924 | Bit line discharge and sense circuit A bit line discharge and sense circuit is provided for use with a static RAM that includes a row and column array of memory cells addressable via first and second bit lines and also a row select line. Each memory cell includes a transistor pair, wherein t... | 04/06/1993 |
| 5140399 | Heterojunction bipolar transistor and the manufacturing method thereof A heterojunction bipolar transistor formed as a collector top or emitter top type. This heterojunction bipolar transistor can operate at high speed and can be fabricated into a semiconductor integrated circuit with ease. The manufacturing method thereof i... | 08/18/1992 |
| 5117391 | Bipolar memory cell array biasing technique with forward active PNP load cell A bipolar memory array arranged in a row and column matrix is responsive to a plurality of word line driver transistors for selecting one row of memory cells thereof. The current flowing through each memory cell is provided by a pair or lateral PNP transi... | 05/26/1992 |
| 5091881 | Multiple port memory including merged bipolar transistors A multiple port memory includes memory cells with merged PNP and NPN bipolar transistors. Each memory cell has a pair of PNP load transistors and a pair of NPN control transistors in a symmetric arrangement. One or more storage ports provides differential... | 02/25/1992 |
| 5083292 | Bipolar random access memory A bipolar random access memory comprises a plurality of memory cells arranged in row and column formation, a plurality of word lines provided in correspondence to respective rows of the memory cells, a plurality of bit lines provided in correspondence to ... | 01/21/1992 |
| 5043939 | Soft error immune memory An alpha radiation immune integrated circuit memory cell has a pair of secondary transistors connected to cross-couple the primary transistors to form a flow, secondary storage node. The secondary transistors are biased to a standby current that, in combi... | 08/27/1991 |
| 5029129 | High-speed bipolar memory system A switched load diode cell has been developed wherein first and second multi-emitter NPN transistors are provided having bases cross coupled to the other's collectors in typical latch fashion as shown in FIG. 5. A PN diode is provided having an anode coup... | 07/02/1991 |
| 5029127 | Bipolar SRAM having word lines as vertically stacked pairs of conductive lines parallelly formed with holding current lines There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a common signal therethrough such as with respect to the ind... | 07/02/1991 |
| 5023835 | Semiconductor memory system for use in logic LSI's A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor substrate and having address signal forming means for formi... | 06/11/1991 |
| 5016214 | Memory cell with separate read and write paths and clamping transistors Two pairs of bit lines are associated with each column of memory cells in a static random access memory (RAM) to provide separate paths for reading and writing operations or to provide a RAM having dual read ports. One pair of bit lines is connected to th... | 05/14/1991 |
