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| Number | Title | Issue Date |
| 8164940 | Read/write structures for a three dimensional memory Read/write structures for three-dimensional memories are disclosed. In one embodiment, a three-dimensional memory includes a plurality of data storage layers fabricated in parallel on top of one another to form a three-dimensional structure. Each data storage layer ... | 04/24/2012 |
| 8023307 | Peripheral signal handling in extensible three dimensional circuits A method for handling peripheral signals in an extensible three dimensional circuit includes forming an extensible three dimensional circuit with a plurality of stacked crossbar arrays and at least one class of traveling lines which travel vertically and laterally t... | 09/20/2011 |
| 7773405 | Magnetic random access memory and operating method of magnetic random access memory A magnetic random access memory includes: a first and second wirings, a plurality of third wirings, a plurality of memory cells and a terminating unit. The first and second wirings extend in a Y direction. The plurality of third wirings extends in an X direction. Th... | 08/10/2010 |
| 7443707 | Magnetic random access memory array with free layer locking mechanism and method of its use A method of using an MTJ MRAM cell element having two magnetization states of greater and lesser stability. During switching, the free layer is first placed in the less stable state by a word line current, so that a small bit line current can switch its magnetizatio... | 10/28/2008 |
| 7405958 | Magnetic memory device having XP cell and Str cell in one chip According to the semiconductor memory device of this invention, an XP type MRAM cell array and an STr type MRAM cell array are formed on a single chip. The XP type MRAM cell array is laid over the STr type MRAM cell array to form a layered structure. The STr type MR... | 07/29/2008 |
| 7383476 | System architecture and method for three-dimensional memory In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub array... | 06/03/2008 |
| 7378698 | Magnetic tunnel junction and memory device including the same A magnetic tunnel junction device includes a magnetically programmable free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layer... | 05/27/2008 |
| 7372757 | Magnetic memory device with moving magnetic domain walls A magnetic memory device includes a plurality of first metal lines arranged in parallel on a substrate and including a plurality of magnetic domains with variable magnetization directions. A plurality of second metal lines is arranged on the substrate perpendicular ... | 05/13/2008 |
| 7369426 | Magnetoresistive memory cell with dynamic reference layer The present invention relates to an arrangement for increasing a relative change in resistance of a magnetoresistive memory cell (17) having in each case a memory layer (1) and a reference layer (3) on both sides of a tunnel barrier (2), ... | 05/06/2008 |
| 7355883 | Magnetoresistance effect element, its manufacturing method, magnetic reproducing element and magnetic memory A magnetoresistance effect element includes a first ferromagnetic layer (1), insulating layer (3) overlying the first ferromagnetic layer, and second ferromagnetic layer (2) overlying the insulating layer. The insulating layer has formed a throu... | 04/08/2008 |
| 7304888 | Reverse-bias method for writing memory cells in a memory array A memory array having memory cells each comprising a diode and a phase change material or antifuse is reliably programmed by maintaining all word lines and bit lines connected to unselected memory cells at intermediate voltages and applying voltages to place the dio... | 12/04/2007 |
| 7289350 | Electronic device with a memory cell The present invention relates to an electronic device comprising a memory cell with a resistive storage element having a first terminal and a second terminal. The resistive storage element can be switched between a first storage state with a first conductivity and a... | 10/30/2007 |
| 7283381 | System and methods for addressing a matrix incorporating virtual columns and addressing layers A system and methods for addressing unique locations in a matrix. According to some embodiments, the system includes a plurality of uniquely addressable locations. A plurality of virtual columns that include a plurality of serially connected switch elements provide ... | 10/16/2007 |
| 7272028 | MRAM cell with split conductive lines A magnetoresistive memory cell includes N magnetoresistive elements conductively connected in series (where N is an integer greater than or equal to two). The magnetoresistive elements, respectively, are positioned between at least two adjacent conductive lines. At ... | 09/18/2007 |
| 7209376 | Stacked semiconductor memory device A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell ... | 04/24/2007 |
| 7205589 | Semiconductor devices fabricated with different processing options A semiconductor device that provides identical functionality and timing characteristics, fabricated with two fabricating options comprised of: a user configurable high cost fabricating option utilizing a set of masking patterns and a process sequence; and a mask pro... | 04/17/2007 |
| 7184293 | Crosspoint-type ferroelectric memory A crosspoint-type ferroelectric memory is provided. In the crosspoint-type ferroelectric memory, a first memory cell array and a second memory cell array are stacked with a first interlayer insulating layer and a second interlayer insulating layer therebetween. The ... | 02/27/2007 |
| 7173848 | Magnetic random access memory with memory cell stacks having more than two magnetic states A magnetic random access memory (MRAM) has memory units or stacks of multiple memory cells arranged in the X-Y plane on the MRAM substrate with each memory unit having four possible magnetic states. Each memory unit is located at an intersection region between two o... | 02/06/2007 |
| 7106639 | Defect management enabled PIRM and method A defect management enabled PIRM including a data storage medium providing a plurality of cross point data storage arrays. Each array provides a plurality of memory cells. The arrays are allocated into separate super arrays, the separate super arrays virtually align... | 09/12/2006 |
| 7102916 | Method and structure for selecting anisotropy axis angle of MRAM device for reduced power consumption A method for determining a desired anisotropy axis angle for a magnetic random access memory (MRAM) device includes selecting a plurality of initial values for the anisotropy axis angle and determining, for each selected initial value, a minimum thickness for at lea... | 09/05/2006 |
| 7081377 | Three-dimensional memory A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels. ... | 07/25/2006 |
| 7071009 | MRAM arrays with reduced bit line resistance and method to make the same Improved MRAM arrays and a method of forming the same are disclosed in which a bit line has thinner portions formed over MTJs and thicker portions therebetween. Bottom electrodes are formed in a first insulation layer on a substrate and then MTJs and a coplanar seco... | 07/04/2006 |
| 7064975 | Magnetic random access memory A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a... | 06/20/2006 |
| 7051251 | Method for storing data in a write-once memory array using a write-many file system The preferred embodiments described herein provide various data allocation and error recovery methods that allow data to be written to a write-once memory array using a write-many file system. Other preferred embodiments described herein relate to methods for genera... | 05/23/2006 |
| 7042753 | Multi-value magnetic random access memory with stacked tunnel magnetoresistance (TMR) elements A memory cell is constituted by a TMR element and a MOS transistor. The source diffusion layer of the MOS transistor is connected to a source line and the drain diffusion layer of the transistor is connected to a TMR element via a local interconnection wire. The TMR... | 05/09/2006 |
| 7026212 | Method for making high density nonvolatile memory An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably compr... | 04/11/2006 |
| 7020004 | Double density MRAM with planar processing The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrate... | 03/28/2006 |
| 7009275 | Method for making high density nonvolatile memory An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably compr... | 03/07/2006 |
| 6995422 | High-density three-dimensional memory An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably compr... | 02/07/2006 |
| 6992910 | Magnetic random access memory with three or more stacked toggle memory cells and method for writing a selected cell A “toggling” type of magnetic random access memory (MRAM) has memory stacks arranged in the X-Y plane on the MRAM substrate with each memory stack having a plurality of toggle memory cells stacked along the Z axis. Each memory stack is located at an intersection... | 01/31/2006 |
| 6990004 | Magnetic random access memory A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a... | 01/24/2006 |
| 6982894 | Three-dimensional magnetic memory array with a minimal number of access conductors therein and methods thereof A structure and method for forming a magnetic memory having a number N of levels of magnetic memory cells by forming a plurality of levels of magnetic memory cells, each level including at least one magnetic memory core structure having first and second surfaces, fo... | 01/03/2006 |
| 6952030 | High-density three-dimensional memory cell A three dimensional monolithic memory comprising a memory cell allowing for increased density is disclosed. In the memory cell of the present invention, a bottom conductor preferably comprising tungsten is formed. Above the bottom conductor a semiconductor element p... | 10/04/2005 |
| 6937071 | High frequency differential power amplifier A differential CMOS amplifier includes two CMOS inverters and biasing circuitry providing feedback loops across the output and input of each inverter. The biasing circuitry provides linear biasing so that the inverters can apply a desired gain to a pair of high freq... | 08/30/2005 |
| 6937495 | Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory ce... | 08/30/2005 |
| 6937497 | Magnetic random access memory with stacked toggle memory cells A “toggling” type of magnetic random access memory (MRAM) has memory stacks arranged in the X-Y plane on the MRAM substrate with each memory stack having a plurality of toggle memory cells stacked along the Z axis. Each memory stack is located at an intersection... | 08/30/2005 |
| 6927467 | Magnetoresistive memory device and method for fabricating the same Embodiments of the invention include magnetoresistive memory cells having magnetic focusing spacers are formed on sidewalls thereof. Therefore, magnetic fields generated by a bit line and a digit line are focused by the magnetic focusing spacers and efficiently tran... | 08/09/2005 |
| 6927430 | Shared bit line cross-point memory array incorporating P/N junctions A shared bit line cross-point memory array structure is provided, along with methods of manufacture. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the ... | 08/09/2005 |
| 6925015 | Stacked memory device having shared bitlines and method of making the same Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of m... | 08/02/2005 |
| 6906947 | In-plane toroidal memory cell with vertically stepped conductors A magnetic random access memory device uses toroid-like magnetic memory cells. An axial opening extends through each of the memory cells and is generally aligned along a first axis. A first conductor and a second conductor pass through the axial opening of each memo... | 06/14/2005 |
