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3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
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| Number | Title | Issue Date |
| 8059444 | Large array of upward pointing P-I-N diodes having large and uniform current A memory is provided that includes a first memory level having a plurality of memory cells. Each memory cell includes a vertically oriented p-i-n diode including a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily dope... | 11/15/2011 |
| RE42310 | Dual-addressed rectifier storage device A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved t... | 04/26/2011 |
| 7933137 | Magnetic random access memory (MRAM) utilizing magnetic flip-flop structures Non-volatile magnetic random access memory (MRAM) devices that include magnetic flip-flop structures that include a magnetization controlling structure; a first tunnel barrier structure; and a magnetization controllable structure that includes a first polarizing lay... | 04/26/2011 |
| 7830694 | Large array of upward pointing p-i-n diodes having large and uniform current A first memory level includes a first plurality of memory cells that includes every memory cell in the first memory level. Each memory cell includes a vertically oriented p-i-n diode in the form of a pillar that includes a bottom heavily doped p-type region, a middl... | 11/09/2010 |
| 7813157 | Non-linear conductor memory A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are sw... | 10/12/2010 |
| RE41733 | Dual-addressed rectifier storage device A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved t... | 09/21/2010 |
| 7660144 | High-performance one-transistor memory cell A memory cell embodiment includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A ... | 02/09/2010 |
| 7593249 | Memory device for protecting memory cells during programming Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cell... | 09/22/2009 |
| 7586773 | Large array of upward pointing p-i-n diodes having large and uniform current An upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium is disclosed. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-t... | 09/08/2009 |
| 7436704 | Non-volatile memory devices and method thereof Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to th... | 10/14/2008 |
| 7429002 | Electrical device with stored data The invention relates to an electrical device with a logic circuit and with a storage medium which is connected to the logic circuit and in which data are stored. The storage medium is provided with a data link via which data can be read out outside the device with ... | 09/30/2008 |
| 7410838 | Fabrication methods for memory cells A memory cell and a method of fabricating the same. A first conductive layer on a substrate is provided and a first type doped semiconductor layer is then formed on the first conductive layer. The first type doped semiconductor layer and the first conductive layer a... | 08/12/2008 |
| 7397061 | Lateral phase change memory A lateral phase change cell may be formed over a semiconductor substrate. The lateral cell, in some embodiments, may be exposed to light so that the same cell may be addressed by both optical and electrical signals. ... | 07/08/2008 |
| 7391638 | Memory device for protecting memory cells during programming Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cell... | 06/24/2008 |
| 7379317 | Method of programming, reading and erasing memory-diode in a memory-diode array A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, f... | 05/27/2008 |
| 7376008 | SCR matrix storage device One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column o... | 05/20/2008 |
| 7359227 | Shared address lines for crosspoint memory A crosspoint memory includes a shared address line. The shared address line may be coupled to cells above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be ma... | 04/15/2008 |
| 7339811 | Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packi... | 03/04/2008 |
| 7339812 | Stacked 1T-memory cell structure This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the h... | 03/04/2008 |
| 7335992 | Semiconductor apparatus with improved yield The semiconductor apparatus includes a pad; a first line layer placed immediately beneath the pad; and a lattice-shaped contact being between the pad and the first line layer. ... | 02/26/2008 |
| 7330367 | Stacked 1T-MTJ MRAM structure This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher ... | 02/12/2008 |
| 7327628 | Circuit and method for reading an antifuse An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and comp... | 02/05/2008 |
| 7327629 | Circuit and method for reading an antifuse An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and comp... | 02/05/2008 |
| 7323708 | Phase change memory devices having phase change area in porous dielectric layer A phase change memory device includes a lower electrode and a porous dielectric layer having fine pores on the lower electrode. A phase change layer is provided in the fine pores of the porous dielectric layer. An upper electrode is provided on the phase change laye... | 01/29/2008 |
| 7317655 | Memory cell array biasing method and a semiconductor memory device A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is ... | 01/08/2008 |
| 7310264 | Rectifying charge storage memory circuit A composite rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, is provided in a memory circuit or memory cell. In one form, the memory cell is adapted for alternative operation as a random access memory (RAM) or as... | 12/18/2007 |
| 7310266 | Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing inform... | 12/18/2007 |
| 7304888 | Reverse-bias method for writing memory cells in a memory array A memory array having memory cells each comprising a diode and a phase change material or antifuse is reliably programmed by maintaining all word lines and bit lines connected to unselected memory cells at intermediate voltages and applying voltages to place the dio... | 12/04/2007 |
| 7289349 | Resistance variable memory element with threshold device and method of forming the same A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least two resistance states. The threshold device is configured to switch from a high resistance state to a lo... | 10/30/2007 |
| 7286414 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controll... | 10/23/2007 |
| 7279772 | Edge intensive antifuse and method for making the same An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 10/09/2007 |
| 7277349 | Circuit and method for reading an antifuse An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and comp... | 10/02/2007 |
| 7277313 | Resistance variable memory element with threshold device and method of forming the same A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least two resistance states. The threshold device is configured to switch from a high resistance state to a lo... | 10/02/2007 |
| 7273809 | Method of fabricating a conductive path in a semiconductor device A method for fabricating an ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally, in which disposable spacers are utilized to fabricate ultra-small pores into which the electrodes are formed.... | 09/25/2007 |
| 7271403 | Isolating phase change memory devices A phase change memory may be made using an isolation diode in the form of a Schottky diode between a memory cell and a word line. The use of Schottky diode isolation devices may make the memory more scaleable in some embodiments. ... | 09/18/2007 |
| 7271440 | Method and apparatus for forming an integrated circuit electrode having a reduced contact area A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A re... | 09/18/2007 |
| 7272059 | Sensing circuit for a semiconductor memory A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a ... | 09/18/2007 |
| 7272067 | Electrically-programmable integrated circuit antifuses Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programmi... | 09/18/2007 |
| 7269898 | Method for making an edge intensive antifuse An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 09/18/2007 |
| 7269080 | Nonvolatile phase change memory device and biasing method therefor A nonvolatile phase change memory device including a memory array formed by memory cells arranged in rows and columns, word lines connected to first terminals of memory cells arranged on the same row, and bit lines connected to second terminals of memory cells arran... | 09/11/2007 |
