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| Number | Title | Issue Date |
| 7995369 | Semiconductor memory device This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the... | 08/09/2011 |
| 7742352 | Variable sense level for fuse-based non-volatile memory Techniques for use with a fuse-based non-volatile memory circuit include digitally controlling a resistance threshold of the circuit. The circuit includes a fuse circuit and a comparator circuit. The comparator circuit is configured to compare a first signal indicat... | 06/22/2010 |
| 7710758 | Multichip system and method of transferring data therein Disclosed is a multichip system and method of transferring data between memory chips in direct. The multichip system includes first and second memory chips, and a host system to control operations of the first and second memory chips. The first memory chip controls ... | 05/04/2010 |
| 7518900 | Memory A memory capable of reducing the memory cell size is provided. This memory includes a plurality of memory cells including diodes, a plurality of bit lines and a first conductive type first impurity region arranged to intersect with the bit lines for functioning as f... | 04/14/2009 |
| 7433224 | System and method for forcing an SRAM into a known state during power-up There is disclosed a static random access memory (SRAM) device that stores an embedded program that is accessible when the SRAM device is powered up. The SRAM device comprises a plurality of storage cells, each of the storage cells comprises a data latch having an i... | 10/07/2008 |
| 7411808 | Method for reading ROM cell A method for reading data stored in a multiple bit memory cell, the memory cell comprising a switch located within an array of switches arranged in columns and rows, each switch having a control node and first and second switched nodes between which the flow of curr... | 08/12/2008 |
| 7394088 | Thermally contained/insulated phase change memory device and method (combined) A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed contact surfaces. A phase change memory element is encased within the di... | 07/01/2008 |
| 7359230 | Nonvolatile memory device Provided is a nonvolatile memory device including: a storage element; a switching element electrically connected to the storage element; and a plurality of lead wirings electrically connected to the switching element, all of which are arranged on a substrate having ... | 04/15/2008 |
| 7358590 | Semiconductor device and driving method thereof A semiconductor device includes a memory with a simple structure, an inexpensive semiconductor device, a manufacturing method and a driving method thereof. One feature is that, in a memory which has a layer including an organic compound as a dielectric, by applying ... | 04/15/2008 |
| 7355879 | Semiconductor integrated circuit, operating method thereof, and IC card including the circuit One main electrode of a TFT is connected with one terminal of a two-terminal type nonvolatile memory element, a gate electrode of the TFT is connected with a word line, and the other main electrode thereof is connected with a bit line. The other terminal of the memo... | 04/08/2008 |
| 7338892 | Circuit carrier and manufacturing process thereof A circuit carrier including a core layer, a passive component, a plurality of dielectric layers, and a plurality of circuit layers is provided. The core layer has a first surface and a second surface. In addition, the core layer has a hole, and the passive component... | 03/04/2008 |
| 7317641 | Volatile memory cell two-pass writing method A method is set forth for writing volatile memory cells embodied on an integrated circuit and taking the form of an array of volatile memory cells including a plurality of word lines and a plurality of bit lines. In use, a first write operation is performed on at le... | 01/08/2008 |
| 7314815 | Manufacturing method of one-time programmable read only memory An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-typ... | 01/01/2008 |
| 7304355 | Three-dimensional-memory-based self-test integrated circuits and methods The three-dimensional memory (3D-M) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, 3D-M has minimum impact to the layout of the CUT. The CUT with integrated 3D-M supports IC self-test. Moreov... | 12/04/2007 |
| 7304888 | Reverse-bias method for writing memory cells in a memory array A memory array having memory cells each comprising a diode and a phase change material or antifuse is reliably programmed by maintaining all word lines and bit lines connected to unselected memory cells at intermediate voltages and applying voltages to place the dio... | 12/04/2007 |
| 7285464 | Nonvolatile memory cell comprising a reduced height vertical diode A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped ... | 10/23/2007 |
| 7283381 | System and methods for addressing a matrix incorporating virtual columns and addressing layers A system and methods for addressing unique locations in a matrix. According to some embodiments, the system includes a plurality of uniquely addressable locations. A plurality of virtual columns that include a plurality of serially connected switch elements provide ... | 10/16/2007 |
| 7283383 | Phase change resistor cell, nonvolatile memory device and control method using the same A nonvolatile memory device features a phase change resistor cell as a cross-point cell using a phase change resistor and a serial diode switch. The phase change resistor has logic data corresponding to a crystallization state changed by the amount of current suppli... | 10/16/2007 |
| 7279772 | Edge intensive antifuse and method for making the same An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 10/09/2007 |
| 7276403 | Selective oxidation of silicon in diode, TFT, and monolithic three dimensional memory arrays The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of ... | 10/02/2007 |
| 7274608 | Semiconductor memory device and a method of redressing a memory cell A semiconductor memory device has a non-auxiliary memory cell, an auxiliary memory cell, a first driver, and a second driver. The non-auxiliary memory cell is connected to a predetermined bit line and a first word line. The auxiliary memory cell is connected to the ... | 09/25/2007 |
| 7269898 | Method for making an edge intensive antifuse An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 09/18/2007 |
| 7266038 | Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units (101a-101n), a select signal generating unit (105) for generating a sel... | 09/04/2007 |
| 7245000 | Electrically isolated pillars in active devices A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at leas... | 07/17/2007 |
| 7235858 | Edge intensive antifuse and method for making the same An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 06/26/2007 |
| 7221586 | Memory utilizing oxide nanolaminates Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region b... | 05/22/2007 |
| 7219271 | Memory device and method for redundancy/self-repair The preferred embodiments described herein provide a memory device and method for redundancy/self-repair. In one preferred embodiment, a memory device is provided comprising a primary block of memory cells and a redundant block of memory cells. In response to an err... | 05/15/2007 |
| 7215563 | Multi-layered memory cell structure A high-density memory device and design method that utilizes some or all of the existing stacked process conductor layers provided by a manufacturing process to enhance the number of available bitlines and/or wordlines within the memory device. The memory device inc... | 05/08/2007 |
| 7212432 | Resistive memory cell random access memory device and method of fabrication A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access memory device comprising a plurality of first current lines; a plurality of second current lines; a plur... | 05/01/2007 |
| 7210224 | Method for forming an antifuse An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 05/01/2007 |
| 7212458 | Memory, processing system and methods for use therewith A memory includes a selected bitline coupled to the array of memory cells. A column multiplexer passes a signal on the selected bitline to a sense amplifier input in response to a column enable signal. A multiplexer output conditioner discharges the sense amplifier ... | 05/01/2007 |
| 7193893 | Write once read only memory employing floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 03/20/2007 |
| 7189634 | Edge intensive antifuse An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel... | 03/13/2007 |
| 7185173 | Column address path circuit and method for memory devices having a burst access mode Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along wit... | 02/27/2007 |
| 7177181 | Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory ce... | 02/13/2007 |
| 7174351 | Method for deleting stored digital data from write-once memory device A digital storage system is coupled to a write-once memory array. File delete commands are implemented by over-writing a destructive digital pattern to at least a portion of the memory cells associated with the file to be deleted. One disclosed system alters the man... | 02/06/2007 |
| 7167397 | Apparatus and method for programming a memory array A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the... | 01/23/2007 |
| 7166509 | Write once read only memory with large work function floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 01/23/2007 |
| 7164147 | Semiconductor memory device and method of fabricating the same Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device includes a heating portion interposed between a transistor and a data storing portion, and a metal interconnection layer connected to the data storing po... | 01/16/2007 |
| 7158220 | Three-dimensional memory system-on-a-chip The present invention provides a three-dimensional memory (3D-M) system-on-a-chip (SoC). It takes full advantage of the difference in the number of interconnect levels between the embedded processor (eP) and embedded memory (eM) in an SoC chip. The un-used interconn... | 01/02/2007 |
