Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7830690 | Memory module thermal management A method is disclosed for implementing a scheme to configure thermal management control for a memory device resident on a memory module for a computing platform. A method is also disclosed for implementing the configured thermal management control. In a run-time env... | 11/09/2010 |
| 7437491 | Clock and data recovery wherein an FB-DIMM is connected to signal path and null and sync frames control the FB-DIMM Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on a signal path by a transmitting component. The one or more null frame... | 10/14/2008 |
| 7388767 | Electrochemical lithography memory system and method Electronic memory devices fabricated using nanolithography techniques enables rapid and reliable storage of data on a substrate. One such device includes a memory access head, which includes a conductive member and an insulative member. The conductive member include... | 06/17/2008 |
| 7372746 | Low voltage sensing scheme having reduced active power down standby current A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and Nsense amplifiers having low threshold voltages (Vth) for low Vcc se... | 05/13/2008 |
| 7339829 | Ultra low power non-volatile memory module An improved ultra-low power NVM module, which exhibits low power consumption and reduced layout area. An array of compact flash memory cells are programmed and erased in response to positive and negative boosted voltages. However, the compact flash memory cells are ... | 03/04/2008 |
| 7315071 | Magnetic RAM A memory element for a magnetic RAM, contained in a recess of an insulating layer, the recess including a portion with slanted sides extending down to the bottom of the recess, the memory element including a first magnetic layer portion substantially conformally cov... | 01/01/2008 |
| 7242215 | Nanoscale latches and impedance-encoded logic for use in nanoscale state machines, nanoscale pipelines, and in other nanoscale electronic circuits Various embodiments of the present invention are directed to implementation and use of logic-state-storing, impedance-encoded nanoscale, impedance-encoded latches that store logic values as impedance states within nanoscale electronic circuits that employ impedance-... | 07/10/2007 |
| 7233798 | Method and apparatus for determining location of a remote unit using GPS To address the need for faster location determination by GPS-equipped units, this application describes embodiments of the present invention that provide GPS-assist data to a remote unit (110) that is determining its location. This GPS assist data is relative... | 06/19/2007 |
| 7209983 | Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation FIFO memory devices are configured to support a pair of hybrid operating modes that enable the FIFO memory device to be depth-expandable with other FIFO memory devices in a collective standard mode of operation. The pair of hybrid operating modes including a first h... | 04/24/2007 |
| 7203161 | Method and apparatus for recovery from faults in a loop network A method and apparatus for recovery from faults in a loop network (500) is provided. The loop network (500) has a plurality of ports (520, 530, 532, 534) serially connected with means for bypassing the ports (520, 530, 532, 534) from the ... | 04/10/2007 |
| 7200031 | Proton and heavy ion SEU resistant SRAM A method and system is disclosed for reducing proton and heavy ion SEU sensitivity of a static random access memory (SRAM) cell. A first passive delay element has been inserted in series with an active delay element in a first feedback path of the SRAM cell, and a s... | 04/03/2007 |
| 7184329 | Alignment of memory read data and clocking Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read oper... | 02/27/2007 |
| 7095661 | Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A sign... | 08/22/2006 |
| 7068819 | System for storing geospecific data A system for storing geospecific data for use by an interactive computing environment utilizes separate terrain height data storage and image data storage. The terrain height data storage stores blocks of terrain height data which are defined as discrete terrain hei... | 06/27/2006 |
| 7068517 | Low height USB interface connecting device and a memory storage apparatus thereof A connecting device with a low height comprises a connector part, and a set of metal terminals. The connector part has a height compatible with the height of an inner space in a standard USB interface slot socket so as to be inserted into the standard USB interface ... | 06/27/2006 |
| 7048556 | Connector cover for communication device An apparatus for protecting an accessory connector (12) on a communication device (10). The communication device can include an opening (14) for providing access to the connector. The apparatus can be a cover (16) attached in a tethered r... | 05/23/2006 |
| 7010387 | Robotic data storage library comprising a virtual port A robotic data storage library comprising a virtual port and a method for providing a virtual port for a robotic data storage library are disclosed. The virtual exit port, for example, comprises one or more storage locations of the library that are defined as a virt... | 03/07/2006 |
| 6977775 | Method and apparatus for crystallizing semiconductor with laser beams Laser beams emitted by a plurality of laser sources are divided into a plurality of sub-beams, which are irradiated onto selected portions of an amorphous semiconductor on a substrate to crystallize the amorphous semiconductor. A difference in diverging angles betwe... | 12/20/2005 |
| 6970749 | Grouped palette stashing Methods and apparatus, including computer program products, implement techniques for representing control functions in a user application. A group of control palettes is provided in an application window of the user application. A user input associates the group of ... | 11/29/2005 |
| 6964501 | Peltier-cooled LED lighting assembly A high-powered lighting assembly includes an easily sealed continuous thermal barrier and a solid-state actively controlled closed-loop refrigeration system to maximize operational efficiencies and increase unit life. The thermal barrier prevents thermal back-flow f... | 11/15/2005 |
| 6949824 | Internal package heat dissipator A technique is provided for dissipating heat from an integrated circuit within a package. A thermally conductive strip may be installed between an integrated circuit and a substrate before packaging. The package is formed from molded epoxy formed around the integrat... | 09/27/2005 |
| 6930900 | Arrangement of integrated circuits in a memory module Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second ro... | 08/16/2005 |
| 6921855 | Analysis program for analyzing electronic musical score An analysis programs, apparatus, and method is provided for analyzing electronic musical scores. The invention relates to analyzing an electronic musical score that designates a desired musical note sequence in electronic musical score data, extracts a musical note ... | 07/26/2005 |
| 6909624 | Semiconductor memory device and test method thereof In recent system LSIs, a plurality of RAMs differing in capacity and in bit width have come to be mounted on a single chip according to the needs on the system side. However, when testing the plurality of RAMs, if the RAMs differ in capacity, they cannot be tested u... | 06/21/2005 |
| 6665201 | Direct connect solid-state storage device The present disclosure relates to a solid-state storage device. In one arrangement, the storage device comprises a memory device comprising one of an atomic resolution storage (ARS) device and a magnetic random access memory (MRAM) device, a controller, a... | 12/16/2003 |
| 6310796 | Dynamic random access memory device and μBGA package using multiple reference voltage pads A dynamic random access memory device and a μBGA package for the device use multiple pads for a reference voltage. The device includes n input receivers, n data input pads, and x reference voltage pads. Each input receiver operates synchronously with a c... | 10/30/2001 |
| 6266280 | Method of programming nonvolatile semiconductor device at low power A method of programming a nonvolatile semiconductor device at low power. A programming operation is performed by applying a high voltage to a gate of a selected memory cell to induce a strong electric field from a semiconductor substrate, applying a groun... | 07/24/2001 |
| 6211559 | Symmetric magnetic tunnel device A symmetric magnetic tunnel device including first and second magnetic tunnel junctions each including a pinned magnetic layer, an insulating tunnel layer and a free magnetic layer stacked in parallel juxtaposition to allow tunneling of electrons through ... | 04/03/2001 |
| 6008709 | Magnetic bubble motion producer Motion of a magnetic bubble material is caused by subjecting magnetic bubbles within the material to a magnetic field gradient. The bubbles respond to the magnetic field gradient by producing forces angled from the direction of the magnetic field gradient... | 12/28/1999 |
| 6002314 | Utilization of magnetic bubbles to produce a motive force Motion of a magnetic bubble material is caused by subjecting magnetic bubbles within the material to a magnetic field gradient. The bubbles respond to the magnetic field gradient by producing forces angled from the direction of the magnetic field gradient... | 12/14/1999 |
| 5327371 | Information recording and reproducing apparatus An information recording and reproducing apparatus which has a memory portion which uses the Bloch lines occurring at the magnetic domain walls at the periphery of magnetic domains present in magnetic garnet films as the information carrier, a drive porti... | 07/05/1994 |
| 5107458 | Bubble memory peripheral system tolerant to transient ionizing radiation A transient ionizing radiation tolerant peripheral system for a magnetic bubble memory includes a transient ionizing radiation tolerant rotating field coil driver and a transient ionizing radiation tolerant function gate controller. Both the transient ion... | 04/21/1992 |
| 4931990 | Hardened bubble memory circuit An economical circuit arrangement permits disruption, during a nuclear event or single event upset, of operation in portions of a bubble memory system and in a computer connected thereto while maintaining integrity of data stored in the bubble memory. Onl... | 06/05/1990 |
| 4835739 | Mass storage bubble memory system A data storage system comprises a plurality of bubble memory chips each having a major loop and minor loops. At least one of the minor loops of each chip is used to store bad loop data for its respective chip. A system controller controls operation of the... | 05/30/1989 |
| 4819205 | Memory system having memory elements independently defined as being on-line or off-line A memory system containing redundant portions for the achievement of high reliability is disclosed. A total of n memory elements are utilized, but only m of the n memory elements may be on-line at any one time. On-line and off-line status of each of the n... | 04/04/1989 |
| 4759020 | Self-healing bubble memories A block replicate magnetic bubble memory organization is disclosed in which a number of storage loops are arranged between write and read tracks. Data in the read track is supplied to a deskewing circuit under the control of one section of an EAPROM so th... | 07/19/1988 |
| 4754429 | Cassette type magnetic bubble memory A cassette type magnetic bubble memory comprise a bubble memory device including a bubble memory chip and lead terminals; a connector having contacts for electrically connecting the bubble memory device to an outside unit; thin flexible printed substrates... | 06/28/1988 |
| 4734884 | Magnetic bubble memory system with function of protecting specific storage area of bubble memory from rewriting A magnetic bubble memory system with a write protecting function is disclosed. In a power on reset mode or initiallizing mode of an information handling system including the bubble memory system, a bubble memory controller directs to and stores in its own... | 03/29/1988 |
| 4734883 | Magnetic bubble memory purge and verification system An arrangement for purging a magnetic bubble memory and providing a visible purge verification utilizes the thermal compensation Z-axis coil for providing a purge field. A power supply, purge switch and current sensitive circuit interrupter are connected ... | 03/29/1988 |
| 4685081 | Peltier junction used for thermal control of solid state devices An electronic device, such as a bubble memory (21), which has a narrow temperature band of operation, is maintained within the narrow temperature band by a Peltier circuit (30). The Peltier circuit (30) includes a Peltier junction (31) which is placed in ... | 08/04/1987 |
