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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 8149331 | Delay stabilization method and apparatus for video format conversion A method for stabilizing delay during conversion between Standard Definition (SD) video and High Definition (HD) video includes the step of establishing an integer divide ratio (M/N) corresponding to a ratio of clock rates with the output and input formats. The outp... | 04/03/2012 |
| 8130321 | Method and a system for calibrating an analogue video interface The invention relates to systems and methods for calibrating an analogue video interface. Due to the lack of pixel clock signal (206) information in the video-handling unit, a sample clock signal (202) needs to be generated, which should correspond wit... | 03/06/2012 |
| 8107008 | Method and system of automatically correcting a sampling clock in a digital video system A method and system of automatically correcting a sampling clock in a digital video system are disclosed. Sampling clocks with different phases are generated and subjected in turn to analog-to-digital conversion (ADC). A difference of at least a pair of neighboring ... | 01/31/2012 |
| 8072542 | Sampling device, display device using sampling device, and camera A correction sampling signal generation circuit is disposed subsequent to a plural-stage sampling signal generation circuit for sequentially generating sampling signals in response to an input timing signal, an extended sampling circuit is disposed subsequent to a p... | 12/06/2011 |
| 7969507 | Video signal receiver including display synchronizing signal generation device and control method thereof A video signal receiver including a display synchronizing signal generation device and control method are disclosed. The video signal receiver includes: a video processor converting an input analog video signal into a digital signal; a display processor scaling the ... | 06/28/2011 |
| 7602445 | Digital transmission system and clock reproducing device Letting fp be the frequency of a pixel clock, fs be the audio sampling frequency, and fa be the frequency of an audio clock to be reproduced, fa=384 fs=(N/M)fp, where N and M are frequency dividing ratios between the pixel clock and the audio clock of a frequency co... | 10/13/2009 |
| 7561205 | Apparatus and method for adjusting a pixel clock frequency based on a phase locked loop An apparatus for adjusting a pixel clock frequency based on a phase locked loop (PLL) includes: a pixel clock generator (11) for generating an actual pixel clock having an actual frequency; a division frequency counter (12) for dividing the actual pixe... | 07/14/2009 |
| 7532250 | Clock generation apparatus A clock generation apparatus is provided with a frequency phase error calculation circuit 120, whereby a clock synchronized with burst lock and a line lock clock can be simultaneously generated by a DTO 121 on the basis of frequency information of a DT... | 05/12/2009 |
| RE40675 | Method and apparatus for automatic pixel clock phase and frequency correction in analog to digital video signal conversion A method An apparatus and system for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the... | 03/24/2009 |
| 7450178 | Display synchronization signal generator in digital broadcast receiver A display synchronization signal generator capable of displaying a stable image regardless of changes in a transmission speed of a received digital broadcast signal in a digital broadcast receiver. The display synchronization signal generator includes a speed differ... | 11/11/2008 |
| 7440702 | Method for transmitting digital image signal, digital image transmitting device, digital image sending device and digital image receiver A multiplexer of a transmission section generates a clock signal by multiplying a reference clock signal of a digital image signal by a predetermined number âKâ. A parallel digital image signal is converted into a serial digital signal on the basis of the clock ... | 10/21/2008 |
| 7425993 | Video signal processing A method of generating an orthogonally sampled video signal based on a line phase measure. In a first aspect the input signal is sampled by a clock locked to the average line frequency of a video input and the resulting samples are time shifted, optionally with or w... | 09/16/2008 |
| 7391416 | Fine tuning a sampling clock of analog signals having digital information for optimal digital display Method and system for fine tuning frequency and phase of a sampling clock of analog signals (R, G, B) having digital information, for sampling the analog signals within an optimal sampling period, enabling optimal display by a digital display device (92). Sma... | 06/24/2008 |
| 7365797 | Display synchronization signal generation apparatus in digital broadcast receiver and decoder A display synchronization signal generation apparatus and method is provided which makes it possible to display a stable image irrespective of changes in transmission speed of a received digital broadcast signal by generating a synchronization signal of an image to ... | 04/29/2008 |
| 7355652 | Inverse tracking over two different clock domains A video decoder in which the video source clock is generated entirely in the digital domain is disclosed herein. By creating a virtual version of the source clock in a numeric oscillator, the amount of noise in the system is substantially reduced. Furthermore, by tr... | 04/08/2008 |
| 7352253 | Oscillator circuit with tuneable signal delay means The invention discloses an oscillator circuit (100, 200, 300, 400), comprising an oscillating element (110, 210, 310, 410) and output means (115, 215, 315, 415) for outputting an oscillation frequency from the oscillating circuit. The circuit fu... | 04/01/2008 |
| 7352297 | Method and apparatus for efficient implementation of digital filter with thermometer-code-like output A technique is disclosed for processing a binary coded signal to generate a thermometer coded signal. Such technique includes the following steps. A binary coded input signal is obtained. A binary arithmetic operation is performed on a least significant bit (LSB) po... | 04/01/2008 |
| 7349510 | Apparatus for data recovery in a synchronous chip-to-chip system An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing refe... | 03/25/2008 |
| 7348955 | Method of controlling display method, display-use signal producing device, display device, and display system for implementing the method The sending party of a display-use image signal adds to a signal representing a display image a control parameter signal composed of a control tag signal specifying a controlled object and control start/end identification signal Ts or Te between a specific parameter... | 03/25/2008 |
| 7333151 | Dot clock synchronization generator circuit A circuit which generates a dot clock synchronized to an external video signal which can ensure a pulse width allowed by a device which is supplied with the dot clock. A high frequency clock is divided to generate a first dot clock, and the phase is initialized in a... | 02/19/2008 |
| 7327400 | Automatic phase and frequency adjustment circuit and method The invention is a circuit and method for automatically adjusting the phase and frequency of a pixel clock derived from analog image data. The circuit includes a phase locked loop circuit adapted to generate a phase locked loop clock responsive to a reference signal... | 02/05/2008 |
| 7319464 | Method and apparatus for adjusting dot clock signal The present invention provides a technique for appropriately adjusting a dot clock for video signals by a simple process. A process of adjusting a phase of the dot clock first obtains two image data by two dot clocks having different phases, carries out a certain op... | 01/15/2008 |
| 7319492 | Open loop subcarrier synchronization system A system and method for synchronizing signals having respective sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal with an associated sub-carrier. Various aspects... | 01/15/2008 |
| 7317451 | Apparatus and method for displaying out-of-range mode An apparatus and method for displaying an out-of-range mode which has a resolution higher than a mode supported by a monitor is provided. The method for displaying an out-of-range mode in monitor displaying includes the steps of (a) sensing received horizontal and v... | 01/08/2008 |
| 7312833 | Channel equalizing apparatus and method for digital television receiver Disclosed is a channel equalizing apparatus and method for a digital television receiver that performs channel equalization using equalizing algorithms. The channel equalizing apparatus includes a channel equalizing section for compensating for channel distortion us... | 12/25/2007 |
| 7310094 | Liquid crystal display and driving method thereof A liquid crystal display device that are adapted to display a certain information to a user when no signal is input after a power was applied to the liquid crystal display device. In the device, a liquid crystal display panel has pixel electrodes arranged in a matri... | 12/18/2007 |
| 7295248 | External synchronous signal generating circuit and phase difference measuring circuit An external synchronous signal circuit comprises: means for measuring a phase difference between the external frame synchronous signal (FRM_SYNC) and the frame synchronous signal (FRM) of the digital video signal; means for generating a signal (EXT_H) having the sam... | 11/13/2007 |
| 7283151 | Pixel clock generation device causing state transition of pixel clock according to detected state transition and phase data indicating phase shift amount A transition detection circuit detects a transition of a state of a pixel clock, and outputs a detection signal according to a timing of the detected state transition. A control signal generation circuit generates a control signal according to the detection signal a... | 10/16/2007 |
| 7277133 | Adjusting pixel clock A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst si... | 10/02/2007 |
| 7275174 | Self-aligning data path converter for multiple clock systems A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (... | 09/25/2007 |
| 7271843 | Method and apparatus for analyzing a digitally converted analogue signal A method for obtaining line synchronization information items from a video signal is proposed. The inventive method is based on convolving the relevant part of an analogue video line signal with a pattern function. The result of the convolution operation is further ... | 09/18/2007 |
| 7268827 | Circuit for transferring a timing signal between circuits having different clock frequencies A timing signal transferring circuit (10) that may be arranged to stably transfer a timing signal (S1) between two video signal processing circuits that may operate at different clock frequencies has been disclosed. A first timing signal (S1) ma... | 09/11/2007 |
| 7268825 | Digital synchronizing generator A sync generator (genlock) (10) for frequency and phase locking an incoming video signal to a system clock (12) includes a digitizer (16, 22) for digitizing the incoming video signal to yield a digitized color sub-carrier burst component. A nume... | 09/11/2007 |
| 7269240 | Multi-port network interface circuit and related method for triggering transmission signals of multiple ports with clocks of different phases A multi-port network interface circuit and relative control method. The multi-port network is used for transmitting a plurality of signals to different nodes (like terminals) of a network via multiple ports of the network interface circuit. The network interface cir... | 09/11/2007 |
| 7263142 | Apparatus and method for synchronizing symbol timing using timing loop controller A timing loop controller for multilevel modulation scheme is disclosed. The timing loop controller includes a first to fourth computing unit for computing a timing error between an input timing of digital signals and a sampling timing; a first to fourth quantization... | 08/28/2007 |
| 7263049 | Semi-synchronous receiver and apparatus for reading information A receiver is described for delivering a data sequence (ak) at a data rate 1/T from an analog signal (Sa), the receiver comprising: a) converting means (40) for generating a received sequence (rn) by sampling the analog signal (Sa) with a sample rate of 1/Ts,... | 08/28/2007 |
| 7257499 | Method and apparatus for determining a frequency for the sampling of an analog signal In a method and an apparatus for determining a frequency for the sampling of an analog signal, which is provided to a digital screen for representing an image on the same, at least two areas succeeding in line direction will be established in the image to be display... | 08/14/2007 |
| 7254185 | Method for recovering a digital data content in a communication system and apparatus for performing the same A method is directed to recovering a digital data content in a communication system, wherein the digital data content has been converted into an analog signal based on a primary clock, at a transmitter for transmitting to a receiver. The method comprises receiving t... | 08/07/2007 |
| 7253844 | Method and arrangement for synchronising on-screen display functions during analog signal reception A method and an arrangement are disclosed for synchronizing on-screen display functions during analog signal reception in a terminal arrangement that is capable of receiving both digital and analog video signals. There are provided means (312, 313) for genera... | 08/07/2007 |
| 7250981 | Video signal processor and video signal processing method which interpolate a video signal using an interpolation factor based on phase information of a selected clock A video signal processor and a video signal processing method which can prevent the length of one period of a clock from being shortened and can output a video signal that is in phase with a reference signal. When a video data signal that has been processed using a ... | 07/31/2007 |
