Quotables
"Transmission of documents via telephone wires is possible in principle, but the apparatus required is so expensive that it will never become a practical proposition."
Dennis Gabor, British physicist
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8164688 | Frequency adjusting apparatus and adjusting method thereof A frequency adjusting method comprises steps of: generating a first adjusting signal according to a frequency of a first output signal; adjusting a frequency of an input signal by using the first adjusting signal to generate the first output signal, so as to adjust ... | 04/24/2012 |
| 8164689 | Synchronizing signal control circuit and synchronizing signal control method A synchronizing signal control circuit includes: a phase detecting section configured to detect a phase difference between a display synchronizing signal and an input synchronizing signal; an adding section configured to add a set value for setting a synchronization... | 04/24/2012 |
| 8059200 | Video clock generator for multiple video formats An integrated video clock signal generator in which a master phase-locked loop (PLL) control circuit uses an off-chip voltage-controlled oscillator (VCO) to produce an on-chip oscillator signal in synchronization with a horizontal reference signal related to a horiz... | 11/15/2011 |
| 7893997 | Method for generating video clock and associated target image frame A method for generating a video clock and an associated target image frame is disclosed. The method generates an output clock signal for outputting a target image frame to a panel according to a frame pixel number and a vertical synchronization signal (Vsync). The t... | 02/22/2011 |
| 7868949 | Circuit arrangement and method for locking onto and/or processing data, in particular audio, T[ele]v[ision] and/or video data In order to further develop a circuit arrangement (100; 102; 104; 106) and a method of locking onto and/or processing data, in particular audio, television and/or video data, by means of at least one phase locked loop (40), wherein phase information is... | 01/11/2011 |
| 7773153 | Frame-based phase-locked display controller and method thereof A frame-based phase-locked display controller used in a display system and method thereof are described. The frame-based phase-locked display controller for displaying a plurality of image frames in a video signal comprises a frame-based phase-locked loop and a sync... | 08/10/2010 |
| 7683972 | Video signal processing apparatus which generates plural clocks and performing video signal processing using the plural clocks A video signal processing apparatus is provided with a first clock generation circuit for generating a first clock synchronized with an input signal; a second clock generation circuit for receiving a set value to be a reference of an output frequency, adding the set... | 03/23/2010 |
| 7599005 | Method for synchronizing video signals A method for synchronizing video signals is provided wherein a synchronization state signal is generated which is descriptive for the synchronization of an output of fields/frames with the respective input of respective fields/frames of an underlying video data scre... | 10/06/2009 |
| 7499106 | Method and system for synchronizing video information derived from an asynchronously sampled video signal A method and system for synchronizing video information derived from an asynchronously sampled video signals provide a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the s... | 03/03/2009 |
| 7440702 | Method for transmitting digital image signal, digital image transmitting device, digital image sending device and digital image receiver A multiplexer of a transmission section generates a clock signal by multiplying a reference clock signal of a digital image signal by a predetermined number ‘K’. A parallel digital image signal is converted into a serial digital signal on the basis of the clock ... | 10/21/2008 |
| 7436456 | Video device and method for synchronising time bases of video devices A video system comprises a first video device which transmits a video signal comprising image information and synchronisation information and a second video device which receives the composite video signal. The second device has a time base. For synchronising the tw... | 10/14/2008 |
| 7432980 | Method for reducing analog PLL jitter in video application The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the fa... | 10/07/2008 |
| 7391416 | Fine tuning a sampling clock of analog signals having digital information for optimal digital display Method and system for fine tuning frequency and phase of a sampling clock of analog signals (R, G, B) having digital information, for sampling the analog signals within an optimal sampling period, enabling optimal display by a digital display device (92). Sma... | 06/24/2008 |
| 7372932 | Locking-status judging circuit for digital PLL circuit A locking-status judging circuit is composed of a comparator that compares a phase error signal with a reference signal for judging whether or not a digital PLL circuit locks on an input signal and outputs a signal “0 (zero)” or a signal “1 (one)”, a selecto... | 05/13/2008 |
| 7368965 | Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clo... | 05/06/2008 |
| 7355652 | Inverse tracking over two different clock domains A video decoder in which the video source clock is generated entirely in the digital domain is disclosed herein. By creating a virtual version of the source clock in a numeric oscillator, the amount of noise in the system is substantially reduced. Furthermore, by tr... | 04/08/2008 |
| 7352755 | Network interface card (NIC) with phase lock rise time control generating circuit A Network Interface Card (NIC) for attaching data terminal equipment to a communications network. The NIC includes a Phase Lock Loop (PLL) with a master delay structure that is operatively coupled to at least one delay line structure. The PLL generates control pulse... | 04/01/2008 |
| 7342945 | Data time difference absorbing circuit and data receiving method and device A data time difference absorbing circuit comprises a memory (36) in which first digital data containing first time reference code data are stored and from which the first digital data are read, a memory (37) in which second digital data containing seco... | 03/11/2008 |
| 7327400 | Automatic phase and frequency adjustment circuit and method The invention is a circuit and method for automatically adjusting the phase and frequency of a pixel clock derived from analog image data. The circuit includes a phase locked loop circuit adapted to generate a phase locked loop clock responsive to a reference signal... | 02/05/2008 |
| 7327401 | Display synchronization signal generation apparatus and method in analog video signal receiver A display synchronization signal generation apparatus and method, which make it possible to display a stable image irrespective of changes of horizontal and vertical frequencies of a received analog video signal in an analog video signal receiver. The display synchr... | 02/05/2008 |
| 7321398 | Digital windowing for video sync separation A processing circuit for a sync signal includes a trial circuit and a windowing circuit. The trial circuit includes a counter that generates a count value proportional to the duration between successive sync pulses. When the count value reaches a trial sync spacing ... | 01/22/2008 |
| 7315661 | Directional interpolation method using DCT information and related device The invention provides a method for interpolating a pixel within an image. The image has a plurality of pixels arranged in a matrix format. The method includes detecting if there is an edge in a block of the image according to a Discrete Cosine Transform (DCT) data ... | 01/01/2008 |
| 7312793 | Liquid crystal display controller In a liquid crystal television, a display controller prevents burning of a liquid crystal panel due to irregularity in a synchronization signal. A counter of a liquid crystal display controller detects a period of a horizontal synchronization signal and a vertical s... | 12/25/2007 |
| 7312833 | Channel equalizing apparatus and method for digital television receiver Disclosed is a channel equalizing apparatus and method for a digital television receiver that performs channel equalization using equalizing algorithms. The channel equalizing apparatus includes a channel equalizing section for compensating for channel distortion us... | 12/25/2007 |
| 7313764 | Method and apparatus to accelerate scrolling for buffered windows Methods and apparatuses to accelerate scrolling for buffered windows. In one aspect of the invention, a method to scroll a buffered window on a data processing system includes: determining a second region of a second pixel image of a window in a frame buffer, which ... | 12/25/2007 |
| 7298916 | Image signal processing apparatus and method When performing A/D conversion on image signals, when reducing noise that is caused by jitter by adjusting the phase of the sampling clocks, even if the input waveform has considerable waveform distortion such as a triangular wave, it is possible to reliably reduce ... | 11/20/2007 |
| 7295248 | External synchronous signal generating circuit and phase difference measuring circuit An external synchronous signal circuit comprises: means for measuring a phase difference between the external frame synchronous signal (FRM_SYNC) and the frame synchronous signal (FRM) of the digital video signal; means for generating a signal (EXT_H) having the sam... | 11/13/2007 |
| 7276945 | Low power and low timing jitter phase-lock loop and method A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. Th... | 10/02/2007 |
| 7277133 | Adjusting pixel clock A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst si... | 10/02/2007 |
| 7275174 | Self-aligning data path converter for multiple clock systems A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (... | 09/25/2007 |
| 7271844 | Frame signal phase adjuster A frame signal phase adjuster comprises units for inputting a parallel clock and a reference signal (22-4 and 22-1); generating a frame signal from the reference signal (22-1), adjusting a phase of the frame signal (22 | 09/18/2007 |
| 7271843 | Method and apparatus for analyzing a digitally converted analogue signal A method for obtaining line synchronization information items from a video signal is proposed. The inventive method is based on convolving the relevant part of an analogue video line signal with a pattern function. The result of the convolution operation is further ... | 09/18/2007 |
| 7268825 | Digital synchronizing generator A sync generator (genlock) (10) for frequency and phase locking an incoming video signal to a system clock (12) includes a digitizer (16, 22) for digitizing the incoming video signal to yield a digitized color sub-carrier burst component. A nume... | 09/11/2007 |
| 7268824 | Method and apparatus for canceling jitter A jitter canceling apparatus is provided for canceling jitter in a video signal. For processing a video signal, using as a reference an internal synchronization signal and an external synchronization signal different from the internal synchronization signal in the j... | 09/11/2007 |
| 7250986 | External output video signal processor The object of the invention is offering an external output video signal processor, which does not need coupling capacitor or clamping circuit. A system controller outputs a video signal by which the sync. tip level and the pedestal level were fixed to a predetermine... | 07/31/2007 |
| 7239355 | Method of frame synchronization when scaling video and video scaling apparatus thereof A video scaling apparatus includes a receiver for receiving incoming video signals having transmitted therein a plurality of incoming frames, each incoming frame having a first plurality of synchronization signals for indicating lines in the incoming frame; a scaler... | 07/03/2007 |
| 7224951 | PMA RX in coarse loop for high speed sampling A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy tha... | 05/29/2007 |
| 7209135 | Image display apparatus The invention provides an image display apparatus that efficiently adjusts a video display even when a change takes place in an input signal. The image display apparatus includes a video input device that receives a video signal, a video display that displays an opt... | 04/24/2007 |
| 7209178 | Optical transfer system having a transmitter and a receiver An optical transfer system having a transmitter and a receiver converts an externally-applied video signal into an optical signal and restores the optical signal to the original video signal The system includes a video controller, a transmitter, a transmission photo... | 04/24/2007 |
| 7199834 | Vertical synchronizing signal generation apparatus and video signal processing apparatus The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for ... | 04/03/2007 |
