Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 7750916 | Memory addressing techniques A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initializing parameters describing the contiguous points in the logical space; configuring a memory addr... | 07/06/2010 |
| 7425961 | Display panel driver unit To provide an inexpensive display panel driver unit with a built-in memory, which is capable of achieving the same operation as that obtained in using a dual port memory by employing a single port RAM without reduction in an operation speed. A reservation buf... | 09/16/2008 |
| 7284828 | Method and apparatus for color formatting in a color printer A printer includes a print engine and a monochrome formatter connected to the print engine and being operatively connectable to a color chip. A monochrome print engine and a monochrome formatter provide a monochrome printer. A color print engine and a monochrome for... | 10/23/2007 |
| 7257547 | Service managing system A service managing system comprises: order terminals for enabling customers to view contents of service items and to order desired items, and being portable and driven by a battery; order-receiving terminals for receiving and indicating orders from the order termina... | 08/14/2007 |
| 7245302 | Processing high numbers of independent textures in a 3-D graphics pipeline Circuits, methods, and apparatus provide for the storage of texture descriptors in a graphics memory. Since the texture descriptors are stored in a graphics memory, they do not need to be stored in the graphics processor itself, thus reducing graphics processor circ... | 07/17/2007 |
| 7221580 | Memory gain cell A memory cell includes: a charge storage element (e.g., capacitor); a switch constructed and arranged to selectively connect the charge storage element to a first data line, responsive to a first select signal; and a gain element having an input connected to receive... | 05/22/2007 |
| RE39529 | Graphic processing apparatus utilizing improved data transfer to reduce memory size A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provi... | 03/27/2007 |
| 7187372 | Image data transmission apparatus and method for image display system An image display system comprises: a transmission device (PC) 10, for transmitting image data upon receiving a drawing command from an OS or an application; and a receiving monitor 40, for displaying, on a high-resolution panel 41, image data re... | 03/06/2007 |
| 7154490 | Display driver, electro-optical device, and electronic appliance A display driver, electro-optical device and electronic appliance are provided that make unnecessary processing that calculates positions in a RAM where display data is to be written according to a mounting state thereof. A display driver includes a mounting state s... | 12/26/2006 |
| 7119772 | Methods for driving bistable electro-optic displays, and apparatus for use therein A gray scale bistable electro-optic display is driven by storing a look-up table containing data representing the impulses necessary for transitions, storing data representing at least an initial state of each pixel of the display, storing data representing temporal... | 10/10/2006 |
| 7112815 | Multi-layer memory arrays Multi-layer memory arrays and methods are provided. A memory array has two or more layers of memory material, each layer of memory material having an array of memory cells. A first contact penetrates through each layer of memory material in a first plane and is elec... | 09/26/2006 |
| 7107429 | Data access in a processor A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array. ... | 09/12/2006 |
| 7102646 | Demand-based memory system for graphics applications A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invent... | 09/05/2006 |
| 7066611 | Alignment with linear array of receptors A beam projector is aligned with a linear array of receptors. An alignment receptor is at each end of the linear array of receptors. A beam is projected from the projector. The beam is swept until the alignment receptors sense the beam. A signal is transmitted upon ... | 06/27/2006 |
| 7043618 | System for memory access in a data processor A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array. ... | 05/09/2006 |
| 7035991 | Surface computer and computing method using the same A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers... | 04/25/2006 |
| 7034792 | RAM-incorporated driver, and display unit and electronic equipment using the same The present invention provides a RAM-incorporated driver that enables the writing of moving-image data to a RAM simultaneously with the writing of still-image data to the RAM. The RAM-incorporated X-driver IC can include first and second bus lines for transferring s... | 04/25/2006 |
| 7015918 | 2-D luma and chroma DMA optimized for 4 memory banks A method for storing data of a plurality of components of an image in a memory system with four banks comprising the steps of (A) placing a first portion of data of a first component of the plurality of components into a first bank of the four banks and (B) placing ... | 03/21/2006 |
| 7017027 | Address counter control system with path switching An address-counter control system includes a counter circuit, path switches, and a control circuit. The counter circuit includes a first series of address counters which corresponds to a non-contiguous region portion and second and third series of address counters w... | 03/21/2006 |
| 6992673 | Memory access device, semiconductor device, memory access method, computer program and recording medium To provide a drawing device with which drawing speed can be increased without escalation of price of it. A drawing device is established as a GPU on an entertainment device to perform the drawing to a frame buffer in terms of one of different interleaved patterns. E... | 01/31/2006 |
| 6989825 | Display control device In order to reduce the power consumed by the circuit when the image data is transferred to a memory in a display means, a write region detecting means 8 is provided to detect the address region in the graphics memory 2 accessed for writing by the image... | 01/24/2006 |
| 6985155 | Memory device and image processing apparatus using same A memory device and an image processing apparatus able to achieve an increase in speed of a region growing algorithm which conventionally involved a long processing time and thereby enabling real time operation, including a memory array comprised of a matrix of a pl... | 01/10/2006 |
| 6975324 | Video and graphics system with a video transport processor A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for extracting audio data. The data transport processor provides PCRs to the v... | 12/13/2005 |
| 6965980 | Multi-sequence burst accessing for SDRAM Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory locations divided into memory pages, where each memory location has a row ad... | 11/15/2005 |
| 6937248 | Pixel array with indirectly associated memory A pixellated device (10), such as a display, has pixel row and column address lines (18,20) for addressing each pixel, thereby providing signal data to each pixel (12) or reading signal data from each pixel. An array of memory cells (22) ... | 08/30/2005 |
| 6912638 | System-on-a-chip controller A system-on-a-chip controller having a first processor and a second processor. The first processor provides control processing and image processing. The second processor provides image processing. The processors receive data from an external source through a data bu... | 06/28/2005 |
| 6903744 | Graphics processing system A system is provided for storing pixel data associated with a predetermined pixel region. The system is configured to store pixel data in a predetermined block of memory along with a fill check bit indicative of whether or not values for each pixel within the pixel ... | 06/07/2005 |
| 6900812 | Logic enhanced memory and method therefore A logic enhanced memory that may be used in a video graphics system is presented. The logic enhanced memory includes an operation block that performs a number of operations on a block-by-block basis such that parallel processing results. The operations performed by ... | 05/31/2005 |
| 6876400 | Apparatus and method for protecting a memory sharing signal control lines with other circuitry An apparatus such as a television signal receiver includes first and second circuit boards. The first circuit board includes a memory, and control circuitry for controlling at least one function of the apparatus. The second circuit board is operably coupled to the f... | 04/05/2005 |
| 6870541 | RAM incorporated display driver for reducing load on display screen control and image display apparatus including the same display driver This invention provides an image display apparatus for displaying data stored in a random access memory (RAM) such as LCD, more specifically a display driver achieving easy and flexible display control such as scroll in a display screen without increasing load on CP... | 03/22/2005 |
| 6870578 | Apparatus and method for sharing signal control lines An apparatus such as a television signal receiver includes first and second circuit boards. The first circuit board includes a first device such as a memory, and control circuitry for controlling at least one function of the apparatus. The second circuit board is op... | 03/22/2005 |
| 6847370 | Planar byte memory organization with linear access A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations). ... | 01/25/2005 |
| 6847410 | Picture data memory device with picture data input channels and picture data output channels A picture data memory device which can be used universally comprises a central picture data memory for storing picture data of a plurality of picture data input channels, in which case the stored picture data can additionally be read out via a plurality of picture d... | 01/25/2005 |
| 6831651 | Checkerboard buffer Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementat... | 12/14/2004 |
| 6831650 | Checkerboard buffer using sequential memory locations Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementat... | 12/14/2004 |
| 6760035 | Back-end image transformation A method to perform image transformations that are simplistic, conducive to miniaturization, and inexpensive to implement is provided. Transformations of an image stored in system memory are carried out by copying the image data, transforming the image data to a sel... | 07/06/2004 |
| RE38471 | Method and apparatus for display image rotation A method and an apparatus for rotating images on a computer system is disclosed. The system includes a processor for accessing an image frame buffer using a set of CPU addresses, a memory for storing the frame buffer, a controller for directing the pixel data of the... | 03/23/2004 |
| 6680736 | Graphic display systems having paired memory arrays therein that can be row accessed with 2(2n) degrees of freedom A semiconductor memory device of a high degree of freedom in column and a graphics display system using the semiconductor memory device as a mapping memory are provided. The semiconductor memory device according to the present invention is comprised of a ... | 01/20/2004 |
| 6670960 | Data transfer between RGB and YCRCB color spaces for DCT interface A method for transferring data between an RGB color space and a YCrCb color space useful for a DCT block-computation engine significantly increases throughput and decreases processor overhead. According to one example embodiment, a DMA function is optimiz... | 12/30/2003 |
| 6628292 | Creating page coherency and improved bank sequencing in a memory access command stream A buffer facilitates reordering of incoming memory access commands so that the memory access commands may be associated automatically according to their row/bank addresses. The storage capacity in the buffer may be dynamically allocated among groups as ne... | 09/30/2003 |
