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| Number | Title | Issue Date |
| RE43235 | Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) tra... | 03/13/2012 |
| 8094161 | Virtualization of graphics resources Graphics resources are virtualized through an interlace between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients... | 01/10/2012 |
| 8089488 | Virtualization of graphics resources Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients... | 01/03/2012 |
| 8072463 | Graphics system with virtual memory pages and non-power of two number of memory elements A graphics system utilizes virtual memory pages and has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory elements. Additionally, a partition swizzling operation is used to adjust the ... | 12/06/2011 |
| RE41967 | Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) tra... | 11/30/2010 |
| 7834882 | Virtualization of graphics resources Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients... | 11/16/2010 |
| 7830394 | Virtualization of graphics resources Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients... | 11/09/2010 |
| 7830395 | Virtualization of graphics resources Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients... | 11/09/2010 |
| 7791613 | Graphics memory switch A graphics device delivers a graphics address to a graphics memory switch that includes a graphics random access memory translator and a graphics memory page table. The graphics memory address is delivered to the graphics memory switch via a point-to-point, packet b... | 09/07/2010 |
| 7768522 | Virtualization of graphics resources and thread blocking Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory... | 08/03/2010 |
| 7705853 | Virtualization of graphics resources Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients... | 04/27/2010 |
| 7663635 | Multiple video processor unit (VPU) memory mapping A system and method for memory mapping in a multiple video processor (multi VPU) system is described. In various embodiments, rendering tasks are shared among multiple VPUs in parallel to provide improved performance and capability with minimal increased cost. In va... | 02/16/2010 |
| 7623134 | System and method for hardware-based GPU paging to system memory One embodiment of the present invention sets forth a technique for processing address page requests in a GPU system that is implementing a virtual memory model. A hardware-based page fault manager included in the GPU system intercepts page faults otherwise processed... | 11/24/2009 |
| 7508398 | Transparent antialiased memory access A system and method for providing antialiased memory access includes receiving a request to access a memory address. The memory address is examined to determine if the memory address is within a virtual frame buffer. If the memory address is within a virtual frame b... | 03/24/2009 |
| 7499057 | Address translation in an integrated graphics environment A method of translating graphics virtual addresses to physical addresses in an integrated graphics processor environment includes receiving a request for a graphics operation from an application. The application may be an application executing in a partition of a vi... | 03/03/2009 |
| 7417639 | Drawing device and information processing apparatus There are provided a drawing device and an information processing apparatus which are capable of reading out texture data from a memory at a high speed. A storage circuit stores respective information items of each of texture pixels constituting the texture data and... | 08/26/2008 |
| 7411591 | Graphics memory switch A graphics device delivers a graphics address to a graphics memory switch that includes a graphics random access memory translator and a graphics memory page table. The graphics memory address is delivered to the graphics memory switch via a point-to-point, packet b... | 08/12/2008 |
| 7404063 | Reclaiming the PCI memory range with minimal memory loss in IA-32 platforms A method for configuring resources in IA-32 computers enables the PCI memory address range to be reclaimed with minimal loss of available physical memory. The BIOS establishes a remap window at the top of physical memory. The remap window corresponds to the PCI memo... | 07/22/2008 |
| 7397477 | Memory system having multiple address allocation formats and method for use thereof A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded to access the addressable memory locations of a first block of memor... | 07/08/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7363465 | Semiconductor device, microcomputer, and electronic equipment A semiconductor device comprising a bus master and a bus slave connected by a second bus is provided. A bus control unit (BCU) comprises a first relative address control circuit that performs a process for requesting the access using a relative address to a semicond... | 04/22/2008 |
| 7363397 | System and method for DMA controller with multi-dimensional line-walking functionality A system and method for a DMA controller with multi-dimensional line-walking functionality is presented. A processor includes an intelligent DMA controller, which loads a line description that corresponds to a shape or line. The intelligent DMA controller moves thro... | 04/22/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7356823 | Method for displaying single monitor applications on multiple monitors driven by a personal computer A direct access driver solves limitations of DirectX operation under the Microsoft architecture when using multiple monitors. The direct access driver allows applications employing DirectX application program interfaces to use hardware acceleration without display e... | 04/08/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7333097 | Display apparatus and method capable of rotating an image A system for translating a portrait-oriented software address to a portrait-oriented yet landscape-configured display address. Based on the orientation of a display device, an address translation system either passes the software address “as is” or translates th... | 02/19/2008 |
| 7324835 | Motherboard and daughterboard multi-swap system with communication module for a GPRS system A multi-swap communication module includes a motherboard and a daughterboard. The motherboard is provided with a plurality of necessary components for maintaining the operation of a wireless communication card and the daughterboard is connectable with the motherboar... | 01/29/2008 |
| 7324106 | Translation of register-combiner state into shader microcode An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by ... | 01/29/2008 |
| 7313764 | Method and apparatus to accelerate scrolling for buffered windows Methods and apparatuses to accelerate scrolling for buffered windows. In one aspect of the invention, a method to scroll a buffered window on a data processing system includes: determining a second region of a second pixel image of a window in a frame buffer, which ... | 12/25/2007 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7310752 | System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 12/18/2007 |
| 7302585 | System for providing a trustworthy user interface The preferred embodiment of the invention comprises a computer system which employs a trusted display processor (260), which has a trusted processor (300) and trusted memory (305, 315, 335, 345) physically and functionally distinct from the proc... | 11/27/2007 |
| 7289347 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 10/30/2007 |
| 7282947 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 10/16/2007 |
| 7278060 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 10/02/2007 |
| 7272682 | Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurali... | 09/18/2007 |
| 7266633 | System and method for communicating the synchronization status of memory modules during initialization of the memory modules A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during in... | 09/04/2007 |
| 7259772 | Apparatus, method, and medium for controlling image orientation An apparatus, method, and medium for controlling image orientation are disclosed. An orientation mode detector measures multi-directional rotational angles of a display panel and determines an orientation mode for original image data based on the measured rotational... | 08/21/2007 |
| 7260685 | Memory hub and access method having internal prefetch buffers A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history lo... | 08/21/2007 |
