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| Number | Title | Issue Date |
| 7397477 | Memory system having multiple address allocation formats and method for use thereof A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded to access the addressable memory locations of a first block of memor... | 07/08/2008 |
| 7388588 | Programmable graphics processing engine A fully programmable graphics processing engine is provided. The graphics processing engine includes three independent, programmable processors that run independent sets of instructions from independent instruction storage facilities. Graphics processing tasks may b... | 06/17/2008 |
| RE40326 | Single chip frame buffer and graphics accelerator A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the ... | 05/20/2008 |
| 7366856 | Method and system to locate a storage device A system, to locate at least two storage devices from among a plurality of storage devices, receives a request for the data item. The request includes a data identifier for the data item. Next, the system generates a start number and a step number based on the data ... | 04/29/2008 |
| 7292209 | System and method of driving an array of optical elements A system and/or method for controlling a display array without the use of row and column drivers. The display elements within the system are configured to maintain an active address signal in response to a received signal containing serially encoded display settings... | 11/06/2007 |
| 7118482 | Game system using game cards and game machine A game system includes a plurality of game cards, a game cartridge and a game machine. Each game card visually portrays a figure of a character, stores ability data for the character, and mechanically readably records an identification code and individuality express... | 10/10/2006 |
| 7106340 | Method for controlling the access to a storage device and a corresponding computer program A method and computer program are provided for controlling access to a memory device wherein, even with a complex data storage structure, access is made to memory areas within the memory device with a minimal number of selection inputs required for selection of a de... | 09/12/2006 |
| 7091981 | Data bus compressing apparatus A bus compression apparatus for compressing data is provided to suppress an EMI signal and to simplify a data bus structure. In the apparatus, the voltage levels of the digital output signals are summed in accordance with the resistance values of the data compressio... | 08/15/2006 |
| 7084923 | Display system having improved multiple modes for displaying image data from multiple input source formats Systems and methods are herein given to effect a multiple mode display system that may accept multiple input image data formats and output several possible image data format. In a first embodiment, an image processing system comprises: an input that receives a plura... | 08/01/2006 |
| 7073035 | Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory controller for controlling access to a memory module, wherein the memory m... | 07/04/2006 |
| 7032083 | Glitch-free memory address decoding circuits and methods and memory subsystems using the same Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes re... | 04/18/2006 |
| 6999376 | Burst read addressing in a non-volatile memory device A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arra... | 02/14/2006 |
| 6985155 | Memory device and image processing apparatus using same A memory device and an image processing apparatus able to achieve an increase in speed of a region growing algorithm which conventionally involved a long processing time and thereby enabling real time operation, including a memory array comprised of a matrix of a pl... | 01/10/2006 |
| 6975324 | Video and graphics system with a video transport processor A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for extracting audio data. The data transport processor provides PCRs to the v... | 12/13/2005 |
| 6963956 | Apparatus and method for pipelined memory operations A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and... | 11/08/2005 |
| 6937247 | Memory control device and method A memory control device and a method of controlling memory transfer. The memory control device has a command decoding device, a compare logic device, a decision device, a frame buffer decode device, a frame buffer range device and a command routing device. The frame... | 08/30/2005 |
| 6876400 | Apparatus and method for protecting a memory sharing signal control lines with other circuitry An apparatus such as a television signal receiver includes first and second circuit boards. The first circuit board includes a memory, and control circuitry for controlling at least one function of the apparatus. The second circuit board is operably coupled to the f... | 04/05/2005 |
| 6870578 | Apparatus and method for sharing signal control lines An apparatus such as a television signal receiver includes first and second circuit boards. The first circuit board includes a first device such as a memory, and control circuitry for controlling at least one function of the apparatus. The second circuit board is op... | 03/22/2005 |
| 6847410 | Picture data memory device with picture data input channels and picture data output channels A picture data memory device which can be used universally comprises a central picture data memory for storing picture data of a plurality of picture data input channels, in which case the stored picture data can additionally be read out via a plurality of picture d... | 01/25/2005 |
| 6831654 | Data processing system A data processing system comprising a block move engine, a memory, a register and a reader. The block move engine may be configured to process data. The memory may be configured to store data in the form of a linked list comprising a plurality of items of control da... | 12/14/2004 |
| 6825841 | Granularity memory column access A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially different column addresses depending on the needs of the device utilizing t... | 11/30/2004 |
| 6816165 | Memory system having multiple address allocation formats and method for use thereof A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag ind... | 11/09/2004 |
| 6801988 | Data buffer for block unit data transfer to SDRAM An initial address register holds a transfer destination address as an initial address. Data is written into an input data register to which a unique address is allocated. The written data is put together into a data block having a predetermined transfer destination... | 10/05/2004 |
| 6697075 | Decoder system capable of performing a plural-stage process A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be... | 02/24/2004 |
| 6593932 | System for implementing a graphic address remapping table as a virtual register file in system memory A system for implementing a graphics address remapping table as a virtual register in system memory. The remappinig table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data usin... | 07/15/2003 |
| 6538656 | Video and graphics system with a data transport processor A video and graphics system uses multiple transport processors to receive compressed data streams to perform PID and section filtering as well as DVB and DES decryption and to demultiplex them. The compressed data streams may include in-band and out-of-ba... | 03/25/2003 |
| 6445394 | Serialized mapped memory configuration for a video graphics chip A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other suitable functions. A multiplexer, configured as a time slicer, s... | 09/03/2002 |
| 6424348 | Application program interface for a graphics system An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and ... | 07/23/2002 |
| 6421058 | Graphics command stream for calling a display object in a graphics system An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and ... | 07/16/2002 |
| 6411301 | Graphics system interface An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and ... | 06/25/2002 |
| 6362824 | System-wide texture offset addressing with page residence indicators for improved performance A method and apparatus are disclosed for achieving improved mipmapped texture mapping performance in computer graphics systems. Page residence indicators obviate the need for address comparisons during texel accessing. A mipmap page number is generated fo... | 03/26/2002 |
| 6278467 | Display memory control apparatus The present invention relates to a display memory control apparatus which can shorten a waiting time in making an access to a VRAM from a CPU without making large a circuit scale and causing an increase of power consumption. A data width of a VRAM is prev... | 08/21/2001 |
| 6104418 | Method and system for improved memory interface during image rendering Aspects for increasing efficiency of memory accesses during graphics rendering are provided. A preferred method aspect includes providing a plurality of memory banks for data, and decoding input signals that indicate accessing of at least one of the plura... | 08/15/2000 |
| 6097404 | Data processing system and image processing system A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and... | 08/01/2000 |
| 6028613 | Method and apparatus for programming a graphics subsystem register set A graphics system includes a graphics processor for rendering graphics primitives with a display list. A host processor generates a display list which includes a command format for loading the display list into a register file. The graphics processor incl... | 02/22/2000 |
| 6020902 | Image data storing method and image data storing device An image data storing device capable of solving a problem involved in a conventional device in that an increasing number of memory bus lines are required which are used for simultaneously reading pixel data from memory elements as the dimension of a scree... | 02/01/2000 |
| 5999197 | Synchronized data processing system and image processing system A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and... | 12/07/1999 |
| 5999200 | Method and apparatus for automatically controlling the destination of a graphics command in a register file A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which in... | 12/07/1999 |
| 5860076 | 48-bit wide memory architecture addressing scheme reconfigurable for 8-bit, 16-bit and 32-bit data accesses A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address locations. Six of the eight 32-bit data groups are address... | 01/12/1999 |
| 5829007 | Technique for implementing a swing buffer in a memory array A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream having a fast rate of through-put to be resynchronized to... | 10/27/1998 |
