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| Number | Title | Issue Date |
| 8026921 | Driving method, driving circuit and driving apparatus for a display system A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory comprises the full table of individual sequences, such as interlacing ... | 09/27/2011 |
| 7965297 | Perfect hashing of variably-sized data A “Variable-Rate Perfect Hasher” maps sparse variable-rate data of one or more dimensions into a hash table using a perfect hash function. In various embodiments, perfect hash tables are populated by first computing offset table address for each data point of a ... | 06/21/2011 |
| 7952589 | Data processing apparatus and method thereof A data processing apparatus generates a memory address corresponding to a first memory, and interpolates data read out from the first memory. The data processing apparatus selects a part of the memory address, checks if the first memory stores data corresponding to ... | 05/31/2011 |
| 7889206 | Direct memory accessing for fetching macroblocks Presented herein are a system, method, and apparatus for retrieving an object from memory. The object can be stored in a manner, such that the first byte of the object and the last byte of the object are in the middle of the memory data words. The object is retrieve... | 02/15/2011 |
| 7782332 | Image displaying device An image displaying device comprises a reproduction list creating unit for creating a group of image data within a prescribed range in which a frame number “1” is included and the frame number increases as a first reproduction list and for creating a group of im... | 08/24/2010 |
| 7583270 | Image processing apparatus An image processing apparatus capable of performing flexible, high speed processing, wherein a memory region emptied due to a change of display resolution can be used as a texture memory, increase of an overhead such as switching pages can be prevented, and a declin... | 09/01/2009 |
| 7542046 | Programmable clipping engine for clipping graphics primitives An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit, a read-only memory that is connected to the clipping unit, a read-write memory that is connected to the clip... | 06/02/2009 |
| 7515159 | Reconfigurable address generation circuit for image processing, and reconfigurable LSI comprising the same A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores imag... | 04/07/2009 |
| 7456839 | Screen creating device A screen creating device includes a screen creating section and an address assigning section. The screen creating section forms a screen including a display element for showing a condition under which data is read out of or written in a region of a memory specified ... | 11/25/2008 |
| 7417639 | Drawing device and information processing apparatus There are provided a drawing device and an information processing apparatus which are capable of reading out texture data from a memory at a high speed. A storage circuit stores respective information items of each of texture pixels constituting the texture data and... | 08/26/2008 |
| 7417600 | Electronic entertainment and communication system A data processing system and method in which, by way of example, a memory system is coupled to a video game program processing system. The video game program processing system has a predetermined address space for executing programs stored in a program memory portio... | 08/26/2008 |
| 7417630 | Display controller, display control method, and image display device A color data signal (DATA) and the control signal (CTL) are supplied from a central processor to a display controller, and an address conversion parameter included in the control signal (CTL) is stored in a control register 5. In accordance with the address c... | 08/26/2008 |
| 7397477 | Memory system having multiple address allocation formats and method for use thereof A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded to access the addressable memory locations of a first block of memor... | 07/08/2008 |
| 7362333 | Graphical manipulation in a mobile wireless device Methods to manipulate the mobile wireless device screen more efficiently are provided. The method and devices allow a graphical user interface to be used more efficiently on a mobile handset with limited processing ability. A graphical user interface can be implemen... | 04/22/2008 |
| 7352372 | Indirect addressing mode for display controller A display controller is provided. The display controller is configured to provide an indirect addressing mode to access a memory location within the display controller. The display controller includes a first pin configured to enable access to one of a register of t... | 04/01/2008 |
| 7349027 | Scan converter The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit ... | 03/25/2008 |
| 7339591 | Method to manage graphics address remap table (GART) translations in a secure system intercepted in order to determine if the modification will result in an aperture memory address mapping to a region of trusted memory. If it is determined that the GART modification will not result in a mapping to a portion of trusted memory, then the GART modificat... | 03/04/2008 |
| 7331928 | Ultrasonic doppler bloodstream measurement device The present invention is for an ultrasonic Doppler blood flow measurement device with which high-speed computation is possible, even when a memory having the characteristic of different read/write speeds in the row direction and the column direction is used for the ... | 02/19/2008 |
| 7268787 | Dynamic allocation of texture cache memory A graphics processing system has a cache which is partitionable into two or more slots. Once partitioned, the slots are dynamically allocatable to one or more texture maps. First, number of texture maps needed to render a given scene is determined. Then, available s... | 09/11/2007 |
| 7256797 | Image processing device with synchronized sprite rendering and sprite buffer An image processing device comprises a decoder, a sprite buffer interface, and a sprite buffer as well as a rendering engine, a frame buffer interface, and a frame buffer, which is characterized by synchronizing the write timing for the sprite buffer with the read t... | 08/14/2007 |
| 7245282 | Addressing multistable nematic liquid crystal devices A method of addressing bistable nematic liquid crystal devices is provided. The method is suitable for implementation using commercially available STN drivers. The method involves applying one of at least two data waveforms simultaneously to each column electrode wh... | 07/17/2007 |
| 7242414 | Processor having a compare extension of an instruction set architecture A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision ... | 07/10/2007 |
| 7228525 | Generic rendering framework Methods and apparatus, including computer program products, for rendering objects. According to one aspect, a program has instructions to receive at run time, in a render manager, a request for rendering a first object and an output destination for rendering the fir... | 06/05/2007 |
| 7200724 | Two dimensional data access in a processor A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specify... | 04/03/2007 |
| RE39529 | Graphic processing apparatus utilizing improved data transfer to reduce memory size A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provi... | 03/27/2007 |
| 7184050 | Dynamic computation of chipset-supported accelerated graphics port aperture sizes Methods and apparatus for use with AGP-capable computer systems are disclosed. Since each AGP-capable chipset can have a unique range of graphics port aperture sizes that it supports, current graphics port aperture drivers are chipset-specific, with hard-coded table... | 02/27/2007 |
| 7180511 | Display control system for displaying image information on multiple areas on a display screen A display control system includes multiple image signal sources and image display devices. At the time of performing control for displaying picture signals from the multiple signal sources connected on respective sending lines to respective multiple areas on screens... | 02/20/2007 |
| 7173629 | Image processor with the closed caption function and image processing method A memory control unit adjusts and sets the address of an image data area in the memory space of a memory and the address of a window area adjacent to the memory area, using a memory controller. The memory control unit stores data, other than image data that is suppl... | 02/06/2007 |
| 7164426 | Method and apparatus for generating texture A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of textu... | 01/16/2007 |
| 7154501 | Method and apparatus for three-dimensional parallax drawing A three dimensional parallax drawing system for use in three dimensional graphics or virtual reality is disclosed. The parallax drawing system includes a three dimensional address generator which generates the original X-axis, Y-axis and Z-axis addresses of an image... | 12/26/2006 |
| 7106340 | Method for controlling the access to a storage device and a corresponding computer program A method and computer program are provided for controlling access to a memory device wherein, even with a complex data storage structure, access is made to memory areas within the memory device with a minimal number of selection inputs required for selection of a de... | 09/12/2006 |
| 7107429 | Data access in a processor A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array. ... | 09/12/2006 |
| 7093157 | Method and system for autonomic protection against data strip loss One aspect of the invention is a method for providing protection from data loss on a storage device. An example of the method includes designating a number n, and identifying a plurality of groups of strips on the storage device, wherein a number of strips in a plur... | 08/15/2006 |
| 7079160 | Method and apparatus using a two-dimensional circular data buffer for scrollable image display A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed linear data buffer is used to store a portion of an entire image. The data buffer is larger than the amoun... | 07/18/2006 |
| 7075546 | Intelligent wait methodology A central processing unit (CPU) configured to apply an intelligent wait methodology is provided. The CPU includes a chip select module that defines a chip select signal associated with an external device. The chip select module includes an address space configured t... | 07/11/2006 |
| 7068239 | Data processing method and system A data processing system and method in which, by way of example, a memory system is coupled to a video game program processing system. The video game program processing system has a predetermined address space for executing programs stored in a program memory portio... | 06/27/2006 |
| 7068250 | Addressing multistable nematic liquid crystal device A method of addressing multistable nematic liquid crystal devices, in particular bistable nematic liquid crystal devices is provided. The method is a line at a time addressing scheme where one of at least two data waveforms is applied simultaneously to each of the c... | 06/27/2006 |
| 7053893 | Position conflict detection and avoidance in a programmable graphics processor using tile coverage data Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after write) hazard may exist. A RAW hazard exists when there is a pending write to a destination locatio... | 05/30/2006 |
| 7051018 | Multimedia search system A database search system that retrieves multimedia information in a flexible, user friendly system. The search system uses a multimedia database consisting of text, picture, audio and animated data. That database is searched through multiple graphical and textual en... | 05/23/2006 |
| 7050063 | 3-D rendering texture caching scheme A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores i... | 05/23/2006 |
