Bizarre Patents
Mountable Printable Placard With Headband
A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
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| Number | Title | Issue Date |
| 7978200 | Raster-order pixel dithering Stochastic dithering may be used to reduce the size of the frame buffer and the complexity of the D/A Converters (DACs) in the drive circuitry that are used in a video display system. Hardware for stochastic dithering can be simplified when pixel data is presented i... | 07/12/2011 |
| 7864185 | Register based queuing for texture requests A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parame... | 01/04/2011 |
| 7847803 | Method and apparatus for interleaved graphics processing The present invention provides for programmable interleaved graphics processing. The invention provides an execution pipeline and a number of registers. Each register holds instructions from a separate program. Instructions from the registers are interleaved in the ... | 12/07/2010 |
| 7821520 | Fragment processor having dual mode register file A new, useful, and non-obvious shader processor architecture having a shader register file that acts both as an internal storage register file for temporarily storing data within the shader processor and as a First-In First-Out (FIFO) buffer for a subsequent module.... | 10/26/2010 |
| 7508396 | Register-collecting mechanism, method for performing the same and pixel processing system employing the same A pixel processing system includes a register-collecting mechanism and a pixel shader. The register-collecting mechanism corrects a first program to a second program. The first program requires a number of first registers. The second program requires a portion of th... | 03/24/2009 |
| 7492371 | Hardware animation of a bouncing image A graphics controller for animating an overlay is described. The graphics controller includes a host interface for communicating with an external processor and a plurality of registers in communication with the host interface. Logic is configured to periodically cha... | 02/17/2009 |
| 7436410 | System and method for programming a controller A system for configuring a chip to perform certain operations is provided. The system includes a CPU. The CPU is in communication with a graphics controller. The graphics controller includes a non-volatile memory for storing a look up table (LUT). The graphics contr... | 10/14/2008 |
| 7426722 | Program code conversion for program code referring to variable size registers A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first ... | 09/16/2008 |
| 7409680 | Program code conversion for a register-based program code A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first ... | 08/05/2008 |
| 7400328 | Complex-shaped video overlay using multi-bit row and column index registers A graphics system reduces fetching from memory of color-key pixels when video pixels from a video-overlay window are displayed. A frame buffer is divided into multi-line, multi-pixel blocks that are arranged in block-rows and block-columns. Each block-row has primar... | 07/15/2008 |
| 7369277 | Image processing apparatus, drawing processing method, and computer program A drawing instruction processor refers to a bit map line table that shows whether the bit arrays in the row unit are the same in the order of concentrations. The drawing instruction processor decides whether dither patterns to be used for the adjacent specified draw... | 05/06/2008 |
| 7366935 | High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described. ... | 04/29/2008 |
| 7355602 | Surrogate stencil buffer clearing Methods and apparatuses for effectively clearing stencil buffers at high speed using surrogate stencil buffer clearing. A hardware register tracks the number of surrogate clears of the stencil buffer since the last actual clear. Bits are reserved in each stencil reg... | 04/08/2008 |
| 7356810 | Program code conversion for program code referring to variable size registers A method for generating an intermediate representation of computer program code written for running on a programmable machine comprises: (i) generating a plurality of register objects for holding variable values to be generated by the program code; and (ii) generati... | 04/08/2008 |
| 7356676 | Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a copr... | 04/08/2008 |
| 7346900 | Register-based program code conversion A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first ... | 03/18/2008 |
| 7339592 | Simulating multiported memories using lower port count memories An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multipl... | 03/04/2008 |
| 7333106 | Method and apparatus for Z-buffer operations In one embodiment, the invention is an apparatus. The apparatus includes a Z-buffer memory. The apparatus also includes a set of bits, each of which corresponds to a block of the Z-buffer memory. The apparatus also includes an initialization (init) register. The app... | 02/19/2008 |
| 7328431 | Program code conversion for a register-based program code A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first ... | 02/05/2008 |
| 7324106 | Translation of register-combiner state into shader microcode An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by ... | 01/29/2008 |
| 7325088 | Management of indexed registers in a system on a chip An electronic system comprises a control unit for ordering the storage of an index value for indexed registers, in an additional index register linked to a defined initiator module, in response to a request to write the index value in an index register linked to the... | 01/29/2008 |
| 7280112 | Arithmetic logic unit temporary registers An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register... | 10/09/2007 |
| 7280111 | API communications for vertex and pixel shaders A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications ... | 10/09/2007 |
| 7233342 | Time and voltage gradation driven display device To provide a display device which is capable of multi-gradation display without complicating the structure of a D/A converter circuit. Of m bit digital video data inputted from the external, upper n bit data is used as voltage gradation information and lower (m−n)... | 06/19/2007 |
| 7196708 | Parallel vector processing A video platform architecture provides video processing using parallel vector processing. The video platform architecture includes a plurality of video processing modules, each module including a plurality of processing elements (PEs). Each PE provides parallel vect... | 03/27/2007 |
| 7193601 | Active matrix liquid crystal display An active matrix LCD defines a display signal period and a reset period in each vertical scan period. The display signal period is a period to write and hold display signals in pixels in response to a row select pulse generated from an output pulse of a first shift ... | 03/20/2007 |
| 7162716 | Software emulator for optimizing application-programmable vertex processing A central processing unit (CPU) including an operating system for executing code segments capable of performing graphics processing on the CPU. Associated therewith is a graphics application specific integrated circuit (ASIC) for performing graphics processing in ac... | 01/09/2007 |
| 7158110 | Digital image processing device A low-cost digital image processing device constructed by using a simplified circuit is provided which is capable of reducing an amount of data of an image to be stored in a frame memory and of being applied to a display panel with a desired level of a resolution. I... | 01/02/2007 |
| 7154490 | Display driver, electro-optical device, and electronic appliance A display driver, electro-optical device and electronic appliance are provided that make unnecessary processing that calculates positions in a RAM where display data is to be written according to a mounting state thereof. A display driver includes a mounting state s... | 12/26/2006 |
| 7142221 | Display drive control device and electric device including display device In a system including a color liquid crystal panel, a drive control device for driving the panel, and a microprocessor, the drive control device reduces the burden on the microprocessor as well as power consumption. In a liquid crystal display drive control device t... | 11/28/2006 |
| 7136068 | Texture cache for a computer graphics accelerator A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, and a cache for texels for use by... | 11/14/2006 |
| 7133047 | Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instru... | 11/07/2006 |
| 7129880 | Auto-zoom sloped ADC The operating characteristics of a dynamic comparator is used to automatically change the resolution of a sloped or ramped analog-to-digital converter (ADC) by switching the comparator on and off between first (slow) and second (fast) clock frequencies and comparing... | 10/31/2006 |
| 7116332 | API communications for vertex and pixel shaders A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications ... | 10/03/2006 |
| 7109987 | Method and apparatus for dual pass adaptive tessellation A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shad... | 09/19/2006 |
| 7088371 | Memory command handler for use in an image signal processor having a data driven architecture Disclosed is an image signal processor for use in an image processing system. The image signal processor includes a local memory to store data and a memory command handler having a plurality of memory address generators. Each memory address generator generates a mem... | 08/08/2006 |
| 7061494 | Method and apparatus for hardware optimization of graphics pipeline functions A method and apparatus for optimizing processing of graphics data. An equation for use in processing graphics data is simplified by identifying variables in the equation that remain constant over a set of repeated operations. This simplified equation is implemented ... | 06/13/2006 |
| 7046308 | Method and apparatus for transmitting digital television data A digital television/local bus interface logic supports handling of digital television (DTV) data with non-tearing. The interface logic provides a dual frame buffer DTV architecture in which a pair of DTV/local bus frame buffers alternate functions: one frame buffer... | 05/16/2006 |
| 7038684 | Rendering process apparatus capable of improving processing speed of overall graphic system An input section inputs vertex data from a host CPU or a geometry process section to a rendering main process section. The rendering main process section performs a rendering process in accordance with the vertex data inputted into the input section. Therefore, the ... | 05/02/2006 |
| 7038653 | Shift resister and liquid crystal display having the same In a shift register and an LCD having the same, the shift register includes stages having odd stages for receiving a first clock signal and even stages for receiving a second clock signal and all stages receive a control signal. Each of the stages includes a pull-up... | 05/02/2006 |
