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| Number | Title | Issue Date |
| 7821519 | Scalable unified memory architecture A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received inst... | 10/26/2010 |
| 7400327 | Apparatus, system, and method for a partitioned memory A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a loca... | 07/15/2008 |
| 7369133 | Apparatus, system, and method for a partitioned memory for a graphics system A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a loca... | 05/06/2008 |
| 7353319 | Method and apparatus for segregating shared and non-shared data in cache memory banks In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or non-shared data accesses are directed to one or more banks designated f... | 04/01/2008 |
| 7337260 | Bus system and information processing system including bus system In a bus connection circuit for connecting buses having different bit widths, number of clock cycles can be reduced, and hardware amount can be reduced. The bus connection circuit connects buses of mutually different bit widths having control lines and data lines co... | 02/26/2008 |
| 7333106 | Method and apparatus for Z-buffer operations In one embodiment, the invention is an apparatus. The apparatus includes a Z-buffer memory. The apparatus also includes a set of bits, each of which corresponds to a block of the Z-buffer memory. The apparatus also includes an initialization (init) register. The app... | 02/19/2008 |
| 7333116 | Data processor having unified memory architecture using register to optimize memory access In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 | 02/19/2008 |
| 7334108 | Multi-client virtual address translation system with translation units of variable-range size A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be u... | 02/19/2008 |
| 7321368 | Electronic system and method for display using a decoder and arbiter to selectively allow access to a shared memory An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the... | 01/22/2008 |
| 7307667 | Method and apparatus for an integrated high definition television controller A method and an apparatus for an integrated high definition television controller are described. The integrated high definition digital television controller includes two or more the following functions in a single chip: MPEG2 Transport, Audio and Video Decoders, Vi... | 12/11/2007 |
| 7295249 | Digital television display control apparatus and method Apparatus for controlling a digital television display, the apparatus comprising a main processor 4, a main memory 5 coupled to said main processor 4 via address and data busses, the main memory 5 being arranged to store at least temporar... | 11/13/2007 |
| 7277098 | Apparatus and method of an improved stencil shadow volume operation The computer graphics system is configured to improve the performance of a stencil shadow volume method for rendering shadows. The apparatus and methods utilize a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompre... | 10/02/2007 |
| 7268785 | System and method for interfacing graphics program modules A system and method for interfacing graphics program modules written to execute on a plurality of functional units of a graphics processor using a shared memory. A central processing unit (CPU) receives a first graphics program module that outputs a first parameter ... | 09/11/2007 |
| 7269832 | Generic virtual device driver A method and apparatus provides for handling communications between an application and a device through a device driver. Calls or commands are used by the device driver to access the hardware that are common to a number of different types of devices that are to be h... | 09/11/2007 |
| 7248267 | Method and apparatus for simulated direct frame buffer access for graphics adapters A method, data processing system, and computer instructions for simulating direct frame buffer access. A request for access to a frame buffer memory is received from an application. A portion of system memory is allocated for use as the frame buffer memory in respon... | 07/24/2007 |
| 7240169 | Protocol for coordinating the distribution of shared memory Methods, systems, and articles of manufacture consistent with the present invention coordinate distribution of shared memory to threads of control executing in a program by using a cooperative synchronization protocol. The protocol serializes access to memory by com... | 07/03/2007 |
| 7233323 | Device and method for varying the row scanning time to compensate the signal attenuation depending on the distance between pixel rows and column driver A display device having a control circuit for changing a time period of applying a signal voltage to each of the signal lines and a scanning voltage to each of the scanning lines within one vertical scanning period (T). The control circuit controls each of horizonta... | 06/19/2007 |
| 7230627 | Optimized memory addressing Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the s... | 06/12/2007 |
| 7185309 | Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in r... | 02/27/2007 |
| 7173627 | Apparatus, method and system with a graphics-rendering engine having a graphics context manager A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context ma... | 02/06/2007 |
| 7173634 | Information displaying system An information displaying system, in which digital information data such as news and a commercial message are displayed with screen data on a display without decreasing the amount of the screen data that are displayed in a working region of the display, is provided.... | 02/06/2007 |
| 7161851 | Method and apparatus for generating multiple system memory drive strengths A system and method for generating multiple drive strengths for one or more output signals of a memory controller operable to control a memory subsystem. The system includes a state machine operable to generate an n-bit output representative of a drive strength oper... | 01/09/2007 |
| 7158141 | Programmable 3D graphics pipeline for multimedia applications A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file... | 01/02/2007 |
| 7158140 | Method and apparatus for rendering an image in a video graphics adapter In accordance with the invention, a video source is received by a first video adapter. The video source is captured in the video memory associated with the first VGA. The stored video source is associated with a window of an existing application. When the window loc... | 01/02/2007 |
| 7152125 | Dynamic master/slave configuration for multiple expansion modules A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of th... | 12/19/2006 |
| 7145568 | Shared translation address caching A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data and a cache adapted to store of locations in physical memory available to the graphics subsystem for storing graphics data and available to a graphics controller cou... | 12/05/2006 |
| 7130935 | System and method for using a switch to route peripheral and graphics data on an interconnect A system and method for using a switch to route graphics data and data for a peripheral data on an interconnect is disclosed. A graphics card includes a switch that is communicatively coupled to a computer system. The switch receives graphics data and data for a per... | 10/31/2006 |
| 7129952 | Core logic circuit of computer system capable of accelerating 3D graphics A core logic circuit which works with a CPU and a main graphics accelerator in a computer system is provided. The core logic chip includes a host controller electrically connected to the CPU for receiving a command from the CPU; an auxiliary graphing engine electric... | 10/31/2006 |
| 7126615 | Color compression using multiple planes in a multi-sample anti-aliasing scheme Systems and methods are provided for compressing computer graphics color data in a system utilizing a multi-sample anti-aliasing scheme using multiple planes for storing color data samples. Each of the planes is configured as a block of contiguous memory. ... | 10/24/2006 |
| 7123267 | Core logic chip conducting multi-channel data transmission An additional data transmission channel is provided between the north bridge chip and the system memory when the graphic accelerator is integrated into the north bridge chip. The additional data transmission channel can be similar to the existent data transmission c... | 10/17/2006 |
| 7116304 | Liquid crystal display apparatus Display data read out from a picture display memory region within a UMA memory is written in a FIFO, and display data is transferred from the FIFO at a timing required by a liquid crystal panel, wherein a timing of reading out display data from the UMA region and a ... | 10/03/2006 |
| 7106347 | Transforming pixel data and addresses In a passive pixel data handling system, pixel data may be transferred to a transfer function, at a given address range. The transfer function may perform a transformation and readdress the pixel data. For example, the data may be received through a media port targe... | 09/12/2006 |
| 7106339 | System with local unified memory architecture and method Local memory associated with one or more companion devices within a system is mapped into a system memory for use by an application processor. ... | 09/12/2006 |
| 7106338 | Method and system for optimal usage of memory for storing scheduling and guiding data in 3D-enabled EPG A system that can store electronic program guide information using 3D graphics is disclosed. In a particular embodiment, a data filter and a text-to-image converter are used for converting filtered data into a set of digital images that are defined as a set of textu... | 09/12/2006 |
| 7089537 | System and method for performing path-sensitive value flow analysis on a program Described is a method and system for performing path-sensitive value flow analysis on a software program. Concrete state and value alias information is tracked along each statement and each relevant path in an abstract program and is stored as a symbolic state in a ... | 08/08/2006 |
| 7081897 | Unified memory organization for power savings Positioning a block of graphics memory within a memory system so as to minimize the number of memory devices and/or banks of memory within memory devices occupied by the block of graphics memory so as to maximize the number of memory devices and/or banks of memory w... | 07/25/2006 |
| 7075539 | Apparatus and method for processing dual format floating-point data in a graphics processing system A computing system has a graphics processor, a graphics memory, main memory, a bridge, and a central processing unit configured to process floating-point data of a first fixed size. An interconnect grid includes communication paths to link the graphics processor, th... | 07/11/2006 |
| 7073033 | Memory model for a run-time environment A memory model for a run-time environment is disclosed that includes a process-specific area of memory where objects in call-specific area of memory and session-specific area of memory can be migrated to at the end of a database call. User-specific objects can be th... | 07/04/2006 |
| 7068847 | High-resolution still picture decoding device A high-resolution still picture decoding device is disclosed, which has a memory device, an image decoder, and a decoding controller. The memory device has a bit-stream buffer, a frame buffer and a temporary buffer. The image decoder and decoding controller decode t... | 06/27/2006 |
| 7064764 | Liquid crystal display control device A FIFO section having a FIFO memory is provided between a memory control section and a CPU_I/F section in a path through which image data outputted from a CPU is written into the video memory. Data necessary for writing the image data is stored into the FIFO section... | 06/20/2006 |
