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| Number | Title | Issue Date |
| 8154556 | Multiple simultaneous unique outputs from a single display pipeline One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitt... | 04/10/2012 |
| 8125491 | Multiple simultaneous unique outputs from a single display pipeline One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitt... | 02/28/2012 |
| 7852344 | System for interleaved storage of video data An apparatus comprising a memory and a coder/decoder circuit. The memory may have a first memory portion and a second memory portion. The coder/decoder circuit may be configured to (i) position a set of atoms across the memory, (ii) define a strip across a portion o... | 12/14/2010 |
| 7612780 | Optimized memory addressing Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the s... | 11/03/2009 |
| 7463267 | System for interleaved storage of video data A method for reading atoms positioned within a memory having a first memory portion and a second memory portions, comprising the steps of (a) positioning the atoms having memory addresses across the memory, (b) defining a strip across a portion of the atoms, (c) des... | 12/09/2008 |
| 7420567 | Memory access method for video decoding A method of storing an array of digital data into a memory. The memory includes a plurality of memory pages, and each memory page has a first memory section and a second memory section. The method includes a first step of dividing the array of digital data into a pl... | 09/02/2008 |
| 7366823 | Method and system for memory access Described herein are a method and system for memory access. As the complexity of digital signal processing applications increases, designs may require multiple memory chips. To optimize the bandwidth of the data being accessed from the memory chips, blocks of data a... | 04/29/2008 |
| 7362484 | Optical scanner package with optical noise reduction The optical scanner package having: an optical scanner device scanning an incident beam and including a scanning mirror and a comb-electrode structure operating the scanning mirror; a package container containing the optical scanner device; and a package window that... | 04/22/2008 |
| 7360035 | Atomic read/write support in a multi-module memory configuration Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given r... | 04/15/2008 |
| 7321368 | Electronic system and method for display using a decoder and arbiter to selectively allow access to a shared memory An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the... | 01/22/2008 |
| 7310120 | Receiver of analogue video signal having means for analogue video signal conversion and method for control of display of video frames A receiver of analogue video signal having means for analogue video signal conversion has a receiving block (201) for receiving a first analogue video signal, a conversion block (202) for conversion of the first analogue signal into a digital signal, a... | 12/18/2007 |
| 7310100 | Efficient graphics pipeline with a pixel cache and data pre-fetching An efficient graphics pipeline with a pixel cache and data pre-fetching. By combining the use of a pixel cache in the graphics pipeline and the pre-fetching of data into the pixel cache, the graphics pipeline of the present invention is able to take best advantage o... | 12/18/2007 |
| 7286134 | System and method for packing data in a tiled graphics memory A tiled graphics memory permits z data and stencil data to be stored in different portions of a tile. The tile may be further divided into data sections, each of which may have a byte size corresponding to a memory access size. ... | 10/23/2007 |
| 7281110 | Random access memory controller with out of order execution A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge... | 10/09/2007 |
| 7239323 | Color display driving apparatus in a portable mobile telephone with color display unit A color display driving apparatus that simultaneously on-screen displays an RGB format color image and a YUV format color image on the same color display unit. A first memory stores YUV data, and a YUV-RGB converter converts YUV data read from the first memory to RG... | 07/03/2007 |
| 7237197 | Method and system for presenting a video stream of a video streaming device A method and system for providing video data to a user on a computer is provided. According to the method and system, a video streaming device attached to the computer provides a video stream that is displayed on the computer. Images that were previously captured wi... | 06/26/2007 |
| 7233335 | System and method for reserving and managing memory spaces in a memory resource System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and pixel types. Memory... | 06/19/2007 |
| 7230627 | Optimized memory addressing Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the s... | 06/12/2007 |
| 7227540 | Image display unit and method of manufacturing the same An MEM unit according to the invention comprises an Si (silicon) substrate 1 having such a thickness as to transmit a visible light therethrough, an insulating layer 2 formed in contact with the upper surface of the Si substrate 1, a lower elect... | 06/05/2007 |
| 7221495 | Thin film precursor stack for MEMS manufacturing This invention provides a precursor film stack for use in the production of MEMS devices. The precursor film stack comprises a carrier substrate, a first layer formed on the carrier substrate, a second layer of an insulator material formed on the first layer, and a ... | 05/22/2007 |
| 7219200 | Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions A method of accessing matrix data of a semiconductor memory having memory banks. The memory banks each having memory cells arranged in X and Y directions, a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction ... | 05/15/2007 |
| 7213089 | System and method for displaying a preview indicating a time-based adjustment of image data or sound data An information processing device for setting a parameter about objective data, comprising an output unit for outputting the objective data, an operation unit for detecting an instruction of a user, an output control unit for altering the parameter value with time in... | 05/01/2007 |
| 7205993 | Checkerboard buffer using two-dimensional buffer pages and using memory bank alternation Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least four memories, each having memory pages, data stored to at... | 04/17/2007 |
| 7190368 | Method and/or apparatus for video data storage An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the f... | 03/13/2007 |
| 7191292 | Logging of level-two cache transactions into banks of the level-two cache for system rollback A plurality of processors on a chip is operated in lockstep. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache. As data is stored in a first bank of the L2 cache, the old d... | 03/13/2007 |
| 7180526 | Transparent compatibility and adaptation to differing format implementations in a computer system A method for improving compatibility between an application program and a display device of a computer system includes: providing a first format in a first frame buffer, the first format compatible with a format for an application program, providing a second format ... | 02/20/2007 |
| 7164520 | Packaging for an interferometric modulator A package is made of a transparent substrate having an interferometric modulator and a back plate. A non-hermetic seal joins the back plate to the substrate to form a package, and a desiccant resides inside the package. A method of packaging an interferometric modul... | 01/16/2007 |
| 7164524 | Optical microelectromechanical device and fabrication method thereof An optical microelectromechanical (MEMS) device includes a conductive layer, a dielectric layer, a reflective layer and a plurality of supporters between the dielectric layer and reflective layer. The supporters are tapers, or inversed tapers, having an acute angle,... | 01/16/2007 |
| 7161728 | Area array modulation and lead reduction in interferometric modulators A light modulator is arranged as an array of rows and columns of interferometric display elements. Each element is divided into sub-rows of sub-elements. Array connection lines transmit operating signals to the display elements, with one connection line correspondin... | 01/09/2007 |
| 7158140 | Method and apparatus for rendering an image in a video graphics adapter In accordance with the invention, a video source is received by a first video adapter. The video source is captured in the video memory associated with the first VGA. The stored video source is associated with a window of an existing application. When the window loc... | 01/02/2007 |
| 7139002 | Bandwidth-efficient processing of video images A technique is described for performing multiple video processing tasks in a single operation, as opposed to serially. For instance, a technique is described for de-interlacing a principal video stream at the same time that at least one video sub-stream is combined ... | 11/21/2006 |
| 7116863 | Thermally actuated wavelength tunable optical filter Provided is a wavelength tunable optical filter of a micro-electro-mechanical system (MEMS). The wavelength tunable optical filter comprises two optical fibers or optical waveguides having their optical axes aligned to each other, two lens for collimating light at l... | 10/03/2006 |
| 7103702 | Memory device A memory device is so adapted that data processing time is not prolonged even when there is little bus width. A DRAM is connected to first to third buffer circuits by buses, which have a bus width of 128 bits, via a selector. The first to third buffer circuits are c... | 09/05/2006 |
| 7099020 | Image processing apparatus switchable from full color mode to monochromatic mode In an image processing apparatus for processing image data in either operation mode of a full color mode or a monochromatic mode having processing speed higher than the full color mode, at least a part of an image processing circuit comprises a rewritable device suc... | 08/29/2006 |
| 7093094 | Random access memory controller with out of order execution A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge... | 08/15/2006 |
| 7088369 | Checkerboard buffer using two-dimensional buffer pages and using bit-field addressing Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; memory devices having memory pages, data stored in parallel and ret... | 08/08/2006 |
| 7085995 | Information processing apparatus and processing method and program storage medium An information processing apparatus for suitably corresponding a plurality of images as an editing object to each of a plurality of scenes constituting scenario data. In the apparatus, when a read button (211) is operated, a material clip (212) as an e... | 08/01/2006 |
| 7072948 | Information retrieval system using an internet multiplexer to focus user selection The invention provides a method and system for receiving incoming information from multiple information sources, both interactive and passive, and for engagingly presenting that information to a recipient on a presentation interface. The system includes a “backgro... | 07/04/2006 |
| 7073041 | Virtual memory translation unit for multimedia accelerators A method and system for virtual memory translation of data represented in a multidimensional coordinate system when the physical memory may be located in more than one physical memory location. The translation of one or more virtual addresses into one or more access... | 07/04/2006 |
| 7068281 | Pixel pages optimized for GLV Methods and apparatus for implementing a pixel page system providing pixel pages optimized for use with a GLV (grating light valve). In one implementation, a system includes: a data source, providing pixel data for pixels in a first order, each pixel in a frame havi... | 06/27/2006 |
