Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 8139072 | Network hardware graphics adapter compression A Video Card with standard video output and a Network Ethernet port output of compressed digital video output that represents the image seen by a monitored computer user. A custom video card software driver is used to set up the dual display video controller configu... | 03/20/2012 |
| 8130229 | Methods and apparatus for image processing at pixel rate Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationshi... | 03/06/2012 |
| 7782329 | Method and apparatus for protected graphics generation Presently disclosed are a method and apparatus for generating graphics in a protected manner by establishing a user graphics partition while in an executive context. Once the user context is established, an operating mode is switched to the user context and then exe... | 08/24/2010 |
| 7675522 | Video signal processing circuit, control method of video signal processing circuit, and integrated circuit A display error occurs upon contention between writing of pixel data in a GRAM and reading of pixel data representing a scanning line including pixels which correspond to the pixel data above. Pixel data corresponding to pixels representing a scanning line stored in... | 03/09/2010 |
| 7598959 | Display controller Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock frequencies and a refresh time period. Power conservation can be enhanced by ... | 10/06/2009 |
| 7532218 | Method and apparatus for memory training concurrent with data transfer operations Embodiments of methods and apparatus for memory training concurrent with data transfers are disclosed. For an example embodiment, data may be transferred from a first memory device to a first partition of a memory controller, and a training operation may be performe... | 05/12/2009 |
| 7382366 | Method, apparatus, system, and graphical user interface for selecting overclocking parameters of a graphics system Overclocking parameters in a graphics system are automatically set. In one embodiment, in response to a user request, overclocking parameters for different sets of overclocking parameters are tested using a graphical stress test to select optimum overclocking parame... | 06/03/2008 |
| 7366931 | Memory modules that receive clock information and are placed in a low power state Embodiments described herein provide a power saving state for a memory system. For example, a memory system may derive clocking information from a training pattern sent over a memory channel. A memory may comprise a link to receive training frames, and circuitry to ... | 04/29/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7349027 | Scan converter The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit ... | 03/25/2008 |
| 7337334 | Network processor power management A programmable state machine is incorporated into the core of a network processor (NP) to monitor the utilization of different processing elements in the NP and to control the power state of each element as a function of past and predicted utilization. The state mac... | 02/26/2008 |
| 7310276 | Memory device and method having data path with multiple prefetch I/O configurations A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to... | 12/18/2007 |
| 7275143 | System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addresses A system, apparatus, and method are disclosed for controlling accesses into memory to minimize sequential accesses to the same bank of memory, at least in part, by characterizing a subset of an address in parallel with address translations associated with those acce... | 09/25/2007 |
| 7260489 | Method of displaying multi-channel waveforms A method of displaying multi-channel waveforms including the steps of: dividing at least one waveform screen in a video memory which is mapped to a display terminal into a plurality of waveform windows, wherein boundaries of each of the windows are defined by a plur... | 08/21/2007 |
| 7254283 | Image processor processing image data in parallel with a plurality of processors In order to efficiently process image data in a circuit dividing single image data into a plurality of data and processing the data with a plurality of MPUs in parallel with each other, the MPUs process image data input through an input image data in parallel with e... | 08/07/2007 |
| 7254729 | Processing system and memory module having frequency selective memory A memory module and an apparatus having a memory module for generating an internal clock synchronized to an external clock, the memory module being operated based on the internal clock as an operation clock and includes a first DLL circuit for generating a first int... | 08/07/2007 |
| 7248266 | 3-D rendering engine with embedded memory A 3-D rendering engine with embedded memory a graphics engine. A graphics engine is disclosed that includes a rendering engine for receiving graphics primitives and converting them to pixel information for transfer to a display, The rendering engine is operable to a... | 07/24/2007 |
| 7239323 | Color display driving apparatus in a portable mobile telephone with color display unit A color display driving apparatus that simultaneously on-screen displays an RGB format color image and a YUV format color image on the same color display unit. A first memory stores YUV data, and a YUV-RGB converter converts YUV data read from the first memory to RG... | 07/03/2007 |
| 7222253 | Dynamic power control for reducing voltage level of graphics controller component of memory controller based on its degree of idleness A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage le... | 05/22/2007 |
| 7221475 | Color image processing apparatus The invention relates to a color image processing apparatus and, more particularly, to adjusting means of a color tone and a sharpness. According to the invention, there is provided a color image processing apparatus characterized by having processing means for perf... | 05/22/2007 |
| 7202882 | Liquid crystal display device A liquid crystal display device employing an overshooting driving method is provided which is capable of reducing memory capacity of a frame memory used to delay input data. The above liquid crystal display device for displaying an image using a liquid crystal panel... | 04/10/2007 |
| 7193549 | Scheme for determining internal mode using MCLK frequency autodetect A method of determining an internal operating mode of an electronic circuit derives multiple comparison rates from a rate of a master clock input, computes one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determines whethe... | 03/20/2007 |
| 7191419 | Method of timing model abstraction for circuits containing simultaneously switching internal signals The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test ... | 03/13/2007 |
| 7176928 | Recovery of a serial bitstream clock at a receiver in serial-over-packet transport A receiver for recovering a serial clock of a transmitter is provided. The receiver comprises a buffer configured to store packets received from the transmitter. The packets may be sent through a packet switched network that may incur packet delay during transmissio... | 02/13/2007 |
| 7170233 | Self light emitting display panel and drive control method therefor In the upper half and a lower half of a display area, scanning is implemented such that the directions of scan selection operations are different from each other. The upper half of the panel is scanned from the upper end to the center of the screen, and at the same ... | 01/30/2007 |
| 7158458 | Method and apparatus for recording/reproducing information with respect to optical recording medium A method and an apparatus are provided, which enable a user's standby time to be shortened or utilized effectively in the course of recording/reproduction of information with respect to an optical disk. Information recorded on a disk is reproduced preferentially, an... | 01/02/2007 |
| 7154465 | Multi-line selection driving method for a super-twisted nematic liquid crystal display having low-power consumption A driving unit for an STN-LCD receives input image data and generates column signal functions for selected row lines according to on/off states of pixels, and row signal functions for the selected row lines according to negative/positive states of row signals. The d... | 12/26/2006 |
| 7151707 | Memory device and method having data path with multiple prefetch I/O configurations A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel t... | 12/19/2006 |
| 7126608 | Graphics processor and system with microcontroller for programmable sequencing of power up or power down operations A graphics processor or display device including a microcontroller that functions as a sequencer, a computer system including at least one such graphics processor or display device, and a microcontroller for use in such a graphics processor or display device. In pre... | 10/24/2006 |
| 7123541 | Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of... | 10/17/2006 |
| 7116304 | Liquid crystal display apparatus Display data read out from a picture display memory region within a UMA memory is written in a FIFO, and display data is transferred from the FIFO at a timing required by a liquid crystal panel, wherein a timing of reading out display data from the UMA region and a ... | 10/03/2006 |
| 7099989 | System and technique to reduce cycle time by performing column redundancy checks during a delay to accommodate variations in timing of a data strobe signal A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an address associated with a write command, decodes the address to provide c... | 08/29/2006 |
| 7088322 | Semiconductor device A semiconductor device capable of displaying a still image with low consumption power is provided. In the semiconductor device incorporated with a semiconductor display device capable of displaying the still image, a memory portion is mounted on a substrate on which... | 08/08/2006 |
| 7089438 | Circuit, system and method for selectively turning off internal clock drivers The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating curr... | 08/08/2006 |
| 7084866 | Display driver apparatus, and electro-optical device and electronic equipment using the same A display driver capable of operating in any one of multiple gradient display modes drives a liquid crystal panel in which the first L common electrodes are simultaneously selected in a first selection period and successive groups of L common electrodes are simultan... | 08/01/2006 |
| 7085941 | Clock control apparatus and method, for a memory controller, that processes a block access into single continuous macro access while minimizing power consumption A clock control apparatus for a memory controller comprises an interface unit which processes a block access to a plurality of banks of an SDRAM as a single continuous macro access in order to perform arbitration of the macro access, the block access externally supp... | 08/01/2006 |
| 7081896 | Memory request timing randomizer Methods and apparatus for changing the timing of memory requests in a graphics system. Reading data from memory in a graphics system causes ground bounce and other electrical noise. The resulting ground bounce may be undesirably synchronized with a video retrace sig... | 07/25/2006 |
| 7053900 | Personal computer system and core logic chip applied to same A personal computer system includes a core logic unit, a graphics accelerator, a first tile converter, a local memory, a second tile converter and a system memory. The core logic unit outputs first image data in a linear mode. The graphics accelerator is in communic... | 05/30/2006 |
| 7038689 | Sparse refresh double-buffering A spatial light modulator having a double-buffering pixel value storage mechanism. A double-buffering mechanism enabling sparse refresh. A double-buffering value storage mechanism suitable for use with a serial or raster value producer and a value consumer, especial... | 05/02/2006 |
| 7030871 | Active matrix display device This invention is directed to the active matrix display device with an imaging speed rapid enough for the moving image display and the small power consumption. The selector makes the switch between the moving image mode, where the image signal consecutively inputted... | 04/18/2006 |
