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| Number | Title | Issue Date |
| 7859437 | Scrambled block encoder A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be l... | 12/28/2010 |
| 7796061 | Distributed decoding device using multi-core processor and method for the same Provided is a distributed decoding device using a multi-core processor, including a multi-core processor that includes a plurality of cores which process data as threads; an MPEG division module that receives MPEG data, extracts decoding information from the MPEG da... | 09/14/2010 |
| 7528747 | Scrambled block encoder A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be l... | 05/05/2009 |
| 7482955 | String matching system and method using bloom filters to achieve sub-linear computation time A string matching system includes a text string, a plurality of patterns, an m-byte search window and a plurality of Bloom filters, wherein the m-byte search window stands for an m-byte sub-string in the text string under inspection. Every Bloom filter comprises sub... | 01/27/2009 |
| 7417570 | Lossless comparative compression and transmission method and system Data is compared with a reference data, which is accessible at a source. The data is then separated into a static part and a dynamic part, wherein the static part is common with the reference data and the dynamic part is not common with the reference data. The dynam... | 08/26/2008 |
| 7397399 | Method and device for transcoding N-bit words into M-bit words with M smaller N The present invention concerns a method for transcoding a N bits word into a M bits word with M | 07/08/2008 |
| 7379502 | Method of converting digital data Disclosed is a method of digital data conversion. The method includes binding input digital data into unit blocks constituted by a plurality of bytes, modulation-coding each byte of the input data blocks by using a code conversion table, and allocating a merging bit... | 05/27/2008 |
| 7369070 | Control of analog to digital conversion for analog I/O boards A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board a... | 05/06/2008 |
| 7369748 | Reproducing apparatus and tracking method A reproducing apparatus comprises detecting means 18 and 19 for detecting levels of pilot signals recorded on tracks from reproduced signals reproduced by magnetic heads 1A, 1B, a calculating means 24 for calculating a ratio betwee... | 05/06/2008 |
| 7369600 | Burst communications apparatus and method using tapped delay lines A communications apparatus and method use tapped delay lines as multiplexers and demultiplexers. In one embodiment, a receiver (100) uses a tapped delay line (110) as a demultiplexer to acquire a burst communication at very high data rates in the range... | 05/06/2008 |
| 7365658 | Method and apparatus for lossless run-length data encoding An apparatus and method for lossless run-length data encoding is disclosed. In the first stage of the method, an input data sequence is transformed without increasing its volume in order to obtain long sequences of identical digits. In the second stage, every such s... | 04/29/2008 |
| 7356737 | System, method and storage medium for testing a memory module A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnec... | 04/08/2008 |
| 7355532 | voltage level coding system and method We describe a voltage level coding system and method. The voltage level coding system includes a level encoder having an input to receive data segments coded using a first code and an output to supply second data codes indicating one of 2N plus at least o... | 04/08/2008 |
| 7348903 | Method and apparatus for enhancing performance of entropy coding, and video coding method and apparatus using the entropy coding performance enhancing method A method and apparatus for enhancing the performance of entropy coding in a multilayer-based codec system are provided. In a variable length coding method for lossless-coding first coefficients among coefficients of a discrete layer and one or more fine granular sca... | 03/25/2008 |
| 7342977 | Serial data transmitter with bit doubling A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of... | 03/11/2008 |
| 7340657 | On-chip high-speed serial data analyzers, systems, and associated methods In an embodiment, a method includes forming a plurality of time/voltage points from a number of voltage values and from a number of time values, generating serialized data having a predetermined number of bits, comparing the serialized data to a set predetermined vo... | 03/04/2008 |
| 7331010 | System, method and storage medium for providing fault detection and correction in a memory subsystem A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the... | 02/12/2008 |
| 7327293 | Compression and data encoding for transmission over a character-based protocol ACARS systems and methods for compiling messages includes a processing device configured for mapping eight-bit characters in an eight-bit character stream into a six bit map to create a generally six-bit character stream. The processing device is further configured ... | 02/05/2008 |
| 7324022 | Data encoding apparatus, data decoding apparatus and data encoding/decoding system A data encoding apparatus extracts valid data to be encoded from received data and encodes the data, and realigns the encoded data in units of a predetermined data width and outputs the data having each unit of the predetermined data width. A data decoding apparatus... | 01/29/2008 |
| 7321321 | Decoding of a restricted m-of-n code A method for communication between a sender and a receiver, including receiving data in the form of an M-of-N code, where the M-of-N code includes a first component of length n1 and a second component of length n2; decoding data in which the fi... | 01/22/2008 |
| 7320094 | Retraining derived clock receivers Systems and methods of retraining a receiver provide for determining a minimum transition density for a derived clock data link to the receiver. A retraining flit is generated based on the minimum transition density. In one approach, the retraining flit is generated... | 01/15/2008 |
| 7305574 | System, method and storage medium for bus calibration in a memory subsystem A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memor... | 12/04/2007 |
| 7305541 | Compression of program instructions using advanced sequential correlation Compressing program binaries with reduced compression ratios. One or several pre-processing acts are performed before performing compression using a local sequential correlation oriented compression technology such as PPM, or one of its variants or improvements. One... | 12/04/2007 |
| 7296129 | System, method and storage medium for providing a serialized memory interface with a bus repeater A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies v... | 11/13/2007 |
| 7292162 | Data coding system and method A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems. ... | 11/06/2007 |
| 7292161 | NB/MB coding apparatus and method using both disparity independent and disparity dependent encoded vectors Techniques for encoding N-binary symbol (NB) source data vectors into M-binary symbol (MB) encoded vectors, M>N>0, are provided. Techniques for decoding are also provided. Exemplary coding and decoding apparatuses are presented, as is an exemplary 8B/10B encoding sc... | 11/06/2007 |
| 7277988 | System, method and storage medium for providing data caching and data compression in a memory subsystem A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller a... | 10/02/2007 |
| 7278089 | System and method for error detection in encoded digital data A receiver is to receive an encoded data block that was encoded using a convolutional encoder and includes source bits and error detection bits. The receiver may include a Viterbi decoder, a de-mapper and an error detection unit. The error detection unit is to deter... | 10/02/2007 |
| 7274315 | Scrambled block encoder A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be l... | 09/25/2007 |
| 7263238 | System and method for incremental and continuous data compression A data compression system and method for that is capable of detecting and eliminating repeated phrases of variable length within a window of virtually unlimited size. ... | 08/28/2007 |
| 7256715 | Data compression using dummy codes Received data is compressed according to an algorithm, which is a modification of the conventional LZW algorithm. A limited number of hash values are formed, and a code memory is searched at locations corresponding to the hash values. If all of the locations contain... | 08/14/2007 |
| 7249273 | Synchronized serial interface Some embodiments provide a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based o... | 07/24/2007 |
| 7246124 | Methods of encoding and combining integer lists in a computer system, and computer software product for implementing such methods A range covering integers of an input list is divided into subsets according to a predetermined pattern. The encoding produces coding data including, for each subset containing at least one integer of the input list, data representing the position of this subset in ... | 07/17/2007 |
| 7239254 | Programmable multi-cycle signaling in integrated circuits A programmable multi-cycle signaling scheme provides synchronous communications over relatively large distances. An input digital data stream is de-multiplexed onto multiple conductors. The digital data stream is recreated at the far end of the conductors. ... | 07/03/2007 |
| 7224595 | 276-Pin buffered memory module with enhanced fault tolerance A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a... | 05/29/2007 |
| 7216217 | Programmable processor with group floating-point operations A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to ret... | 05/08/2007 |
| 7210056 | Low latency comma detection and clock alignment An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel g... | 04/24/2007 |
| 7205911 | Apparatus and method for 8B/10B code-group validity check An apparatus and method for checking validity of an 8B/10B code-group are provided. The apparatus for checking validity of an 8B/10B code-group includes a 6B/5B disparity classification unit, a 4B/3B disparity classification unit, an RD6 detection unit, an RD4 detec... | 04/17/2007 |
| 7199732 | Data converter with reduced component count for padded-protocol interface A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes mo... | 04/03/2007 |
| 7197622 | Efficient mapping of signal elements to a limited range of identifiers Signal elements are mapped to a limited range of identifiers by emulating a “virtual” space of identifiers larger than the real limited space of identifiers. The larger virtual identifier space is implemented by an intermediate memory, which provides storage of ... | 03/27/2007 |
