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| Number | Title | Issue Date |
| 7432833 | Data compression system and methods Systems and methods for providing fast and efficient data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises the steps of: analyzing a data block of a... | 10/07/2008 |
| 7290024 | Methods and apparatus for performing mathematical operations using scaled integers Methods, apparatus, and articles of manufacture for performing mathematical operations using scaled integers are disclosed. In particular, an example method identifies a scaled-integer value and determines a multiplier value and a scale value based on the scaled-int... | 10/30/2007 |
| 7277490 | Apparatus for converting PCM signal An apparatus for converting pulse code modulation (PCM) signals in a telecommunication system between two different modulation standards. In the apparatus, a channel selector generates a channel select signal for identifying at least one channel of the multiple chan... | 10/02/2007 |
| 7224838 | Method and apparatus for recovery of encoded data using central value The present invention provides a method for comprising data by determining a central value that is greater than the minimum value and less than the maximum value of the range of data. In one embodiment, the central value is chosen to be a value that substantially re... | 05/29/2007 |
| 7096318 | Content-addressable (associative) memory devices A compound associative memory for use with a data-parallel computer, and a method of storing/retrieving data in the compound associative memory is disclosed. The memory comprises a bit-parallel word-organized associative memory having an array of associative memory ... | 08/22/2006 |
| 7054850 | Apparatus and method for detecting or recognizing pattern by employing a plurality of feature detecting elements A pattern detecting apparatus has a plurality of hierarchized neuron elements to detect a predetermined pattern included in input patterns. Pulse signals output from the plurality of neuron elements are given specific delays by synapse circuits associated with the i... | 05/30/2006 |
| 7031993 | Method and apparatus for fast natural log(X) calculation A method for computing a natural logarithm function includes partitioning a mantissa region between 1 and 2 into N equally spaced sub-regions; precomputing a reference point ai of each of the N equally spaced sub-regions, where i=0, . . . ,N−1; selectin... | 04/18/2006 |
| 6501404 | System and method for encoding an input data stream by utilizing a predictive, look-ahead feature A method compares an input value of the input signal stream with an output value of an integration function of a previous binary value to generate a new binary value based upon the comparison. The method then stores a plurality of successive binary values... | 12/31/2002 |
| 6407680 | Distributed on-demand media transcoding system and method A system and method for the on-demand transcoding of media content from a source type to a destination type is provided, wherein the system includes a plurality of transcoders for transcoding from a plurality of source types to a plurality of destination ... | 06/18/2002 |
| 6377193 | System for converting between non-logarithmic values and logarithmic values An audio signal processor for processing 1-bit signals, comprises an input 40 for receiving a 1-bit signal, means 41, 42 for applying a predetermined filter characteristic to the 1-bit signal whereby the signal is also converted to an n-bit signal where n... | 04/23/2002 |
| 6065031 | Log converter utilizing offset and method of use thereof A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper ... | 05/16/2000 |
| 5968137 | Method of testing a protocol converter with the help of an identical converter and deactivating selection means for preventing asymmetry conversion A method for testing protocol converters is presented, which permits the achievement of a test of all commands, independently of a corresponding test system. A modified protocol converter itself is used for the test. With the help of this method, a test f... | 10/19/1999 |
| 5822721 | Method and apparatus for fractal-excited linear predictive coding of digital signals A method for encoding and decoding digital signals, particularly speech signals, by separating the original signal into a linear and nonlinear portions, the nonlinear portion may have linear aspects. The linear portion is encoded by LPC techniques and the... | 10/13/1998 |
| 5726924 | Exponentiation circuit utilizing shift means and method of using same A circuit and method for computing an exponential signal xg is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts ... | 03/10/1998 |
| 5703801 | Logarithm/inverse-logarithm converter utilizing second-order term and method of using same A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, a multiplier, and two adders. The memory stores a plurality of parameters and second-order terms which are de... | 12/30/1997 |
| 5642305 | Logarithm/inverse-logarithm converter and method of using same A converter, which may be used for implementing either logarithmic or inverse-logarithmic functions, includes a memory, a multiplier, and an adder. The memory stores a plurality of parameters which are derived using a least squares method to estimate a lo... | 06/24/1997 |
| 5629884 | Log converter utilizing offset and method of use thereof A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper ... | 05/13/1997 |
| 5604691 | Logarithm/inverse-logarithm converter utilizing a truncated Taylor series and method of use thereof A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, two multiplier, and two adders. The memory stores a plurality of coefficient which are based on a second-orde... | 02/18/1997 |
| 5600581 | Logarithm/inverse-logarithm converter utilizing linear interpolation and method of using same A converter which may be used for implementing either logarithmic or inverse-logarithmic functions includes a memory, a multiplier, and an adder. The memory stores a plurality of pre-computed values which are used in an interpolation to estimate a logarit... | 02/04/1997 |
| 5553012 | Exponentiation circuit utilizing shift means and method of using same A circuit and method for computing an exponential signal xg is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts ... | 09/03/1996 |
| 5535174 | Random access memory with apparatus for reducing power consumption A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are produced to turn on the current sources involved in activat... | 07/09/1996 |
| 5524089 | Logarithm computing circuit for fixed point numbers A logarithm computing circuit for fixed point numbers is disclosed that has: a shift number detection circuit that inputs a number of a fixed point representation, detects a shift number of the inputted number for the purpose of dividing the inputted numb... | 06/04/1996 |
| 5486826 | Method and apparatus for iterative compression of digital data Data compression is effected on arbitrary high entropy digitized data by compression and entropy transformation in an iterative system. Compression includes nonlinear addressing. Entropy transformation may involve any of a number of techniques to reorder ... | 01/23/1996 |
| 5365465 | Floating point to logarithm converter A method converts an n-bit floating point number to a logarithmic representation, the number having a first set of bits assigned to a mantissa, and a second set of bits assigned to an exponent. The logarithmic representation has a characteristic and a fra... | 11/15/1994 |
| 5343500 | Non-linear encoder and decoder for information transmission through non-linear channels In order to mitigate against the multiplicative noise effects caused by known non-linearities in a trellis coded data transmission system, a signal constellation is formed by starting with a base constellation whose number of signal points and whose geome... | 08/30/1994 |
| 5268684 | Apparatus for a neural network one-out-of-N encoder/decoder An artificial network for encoding the binary on-state of one-out-of-N inputs, say j, when only one state is on at a time wherein the jth on-state is represented by a suitable output level of an N-input MP type neuron operating in the non-saturated region... | 12/07/1993 |
| 5212481 | Circuit for code converting PCM codes A circuit for converting a 8-bit μLawPCM code into a 14-bit linear code comprising an inversion circuit receiving a 8-bit μLawPCM code for outputting a 8-bit inverted signal. A 6-bit signal is obtained by putting a bit of "1" at a place lower than the l... | 05/18/1993 |
| 5047768 | Data companding method and data compressor/expander A data companding method instantaneously compands the 14-bit digital audio signals to be outputted from a satellite broadcast receiver and so on is realized with the given conversion rule, which has a superior companding characteristics across the whole i... | 09/10/1991 |
| 4897652 | Method of coding numbers in binary form A coding method uses a pseudo-logarithmic compression law approximated by a straight line segment curve. Its code word on n+1 binary digits, where n is a positive invariant integer, has a lefthand part made up of a variable number p of binary digits havin... | 01/30/1990 |
| 4896353 | Apparatus for fast decoding of a non-linear code The present invention provides a high-speed decoder for decoding signals encoded into Nordstrom-Robinson 16,256,6 non-linear code. The novel decoder receives a transmitted encoded signal in the form of a multi-dimensional vector to be decoded. The decoder... | 01/23/1990 |
| 4855741 | Logarithmic digital level display device A digital level display in which a digital input signal has its highest order non-zero part logarithmically converted by a first decoder and its lower order part logarithmically converted by a second decoder. The outputs of the two decoders are added to b... | 08/08/1989 |
| 4845497 | Conference circuit for a digital communication system A 001 conference circuit for a digital communication system in which the analog-to-digital and digital-to-analog converters of at least two subscriber terminal stations have different bandwidth of their processable analog signals or in the code format of ... | 07/04/1989 |
| 4791403 | Log encoder/decorder system A high speed form of finite precision binary arithmetic coding comprises encoding/decoding performed in the logarithm domain, resulting in facilitated computation based on additions and subtractions rather than multiplications and divisions. In encoding a... | 12/13/1988 |
| 4626825 | Logarithmic conversion apparatus A logarithmic converting apparatus for converting a digital binary integer into logarithmic representation and for converting logarithmic representation into digital binary integer is disclosed. The apparatus determines the bit position of a leading non-z... | 12/02/1986 |
| 4614935 | Log and antilog functions for video baseband processing The log encoder includes means for determining a number r corresponding to the position of the most significant one in the respective input samples, and generating an equivalent binary value. To the binary value is added a predetermined value when the inp... | 09/30/1986 |
| 4608554 | Asynchronous parallel fixed point converter An electronic circuit is used as an asynchronous floating point converter to process data. Data words are received and processed by the floating point converter to produce processed output data. The function for processing is software selectable and may b... | 08/26/1986 |
| 4603323 | Method for extending the exponent range of an IBM 370-type floating point processor A method for extending the exponent range in an IBM System/370-type floating point arithmetic processor. Very large or very small numbers are represented by a pair of words having sign, exponent, and fraction portions thereof. If the signs of the low- and... | 07/29/1986 |
| 4595907 | PCM data translating apparatus An interface device for use between a North American PCM channel bank and a CCITT PCM channel bank which allows data to stay in digital format rather than being converted to voice frequency. The interface takes care of not only the completely different se... | 06/17/1986 |
| 4583180 | Floating point/logarithmic conversion system A digital transformation system for converting between logarithm functions and floating point functions very quickly by normalizing the floating point number in the range of one to two, and adapting one function as the other function, after a correction, ... | 04/15/1986 |
| 4544919 | Method and means of determining coefficients for linear predictive coding An improved method and means of determining reflection coefficients that characterize an electrical signal that obtains characteristics of an all-zero inverse lattice filter. The reflection coefficients are obtained by filtering the signal, sample the fil... | 10/01/1985 |
