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Class 340/2.21 - Plural stages


Subclass of Class 340 - Communications: electrical
Definition: Subject matter including multiple levels of plural matrices
No. of patents: 87
Last issue date: 05/18/2010


1      
NumberTitleIssue Date
7719405Crosspoint switch with low reconfiguration latency
A method of operating a circuit for processing a digital signal is disclosed. The circuit includes various circuit stages having respective enabled states. A present signal path is established which includes circuit stages in their respective enabled states. Power i...
05/18/2010
7424011Rearrangeably nonblocking multicast multi-stage networks
A rearrangeably nonblocking multicast network includes an input stage having r1 switches and n1 inlet links for each of r1 switches, an output stage having r2 switches and n2 outlet links for each of r2
09/09/2008
7356737System, method and storage medium for testing a memory module
A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnec...
04/08/2008
7331010System, method and storage medium for providing fault detection and correction in a memory subsystem
A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the...
02/12/2008
7310333Switching control mechanism for supporting reconfiguaration without invoking a rearrangement algorithm
A method of modeling or constructing a switch element uses an ingress stage with input sorters and input routers; an egress stage with output routers and output sorters; and a center stage interconnecting the ingress and egress stages. Routers are partitioned such t...
12/18/2007
7305574System, method and storage medium for bus calibration in a memory subsystem
A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memor...
12/04/2007
7296129System, method and storage medium for providing a serialized memory interface with a bus repeater
A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies v...
11/13/2007
7280538Multicast concentrators
A multicast concentrator to both concentrate and multicast packets, and the concomitant self-routing control mechanism for the switching of the packets in the multicast concentrator. An m-to-n multicast concentrator always guarantees that the total number of 0-bound...
10/09/2007
7277988System, method and storage medium for providing data caching and data compression in a memory subsystem
A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller a...
10/02/2007
7277428Multiple stage cross connect switch
A cross connect switch has a plurality of stages. Each stage has a plurality of packers, a plurality of memory portions and a plurality of multiplexers. Each packer receives input data and provides the input data as a set of contiguous valid data. The multiplexers d...
10/02/2007
7230927Non-blocking expandable call center architecture
An improved call center architecture includes a switch which communicates with agents either over a broadband network or through a conventional legacy PBX. The hybrid configuration also includes N+1 fault tolerance and the ability to linearly expand the capacity of ...
06/12/2007
7205881Highly parallel switching systems utilizing error correction II
An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage n...
04/17/2007
7190412Video switching systems and methods
Systems and methods for performing video switching between multiple inputs and outputs are disclosed. In one embodiment, a system includes a video box coupled to one or more user interfaces, a plurality of video inputs, and a plurality of video outputs. The video bo...
03/13/2007
7184432Switch fabric architecture and techniques for implementing rapid hitless switchover
A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routing each frame ...
02/27/2007
7142521Wireless packet data distributed communications system
A two-way satellite communications system includes an Earth station communicating with a plurality of remote terminals using a network access protocol that facilitates low power consumption by the terminals. The earth station generates forward link TDM packet data t...
11/28/2006
7113506Butterfly network with switches set for two node disjoint paths and method for forming the paths
In a butterfly network, a number of switches are set to provide two paths that are independent of each other, from a first switch to a second switch, and from the first switch to a third switch respectively. Identification of switches to be set from among all switch...
09/26/2006
7106728Switching by multistage interconnection of concentrators
A method and apparatus for performing switching by multistage interconnection of switching elements with improved performance and low layout complexity is disclosed. The techniques of line grouping, concentrators, self-route control through sorting are applied to re...
09/12/2006
7103059Scalable 2-stage interconnections
Modifications to the 2-stage interconnection to allow flexible scalability. Different switching fabrics having a range of different sizes can be constructed out of the same set of I/O switching nodes through this modified 2-statge interconnection, which can further ...
09/05/2006
7072334Physical implementation of switching fabrics constructed from recursive 2-stage interconnection
Physical implementation of the switching fabric of a massive broadband switching network constructed from recursive 2-stage interconnection. The recursive 2-stage construction is realized through a hierarchical levels of implementation, including inside-chip impleme...
07/04/2006
7065101Modification of bus protocol packet for serial data synchronization
An apparatus for enabling transmission of parallel data from a first parallel bus to a second parallel bus via a serial data channel includes a first logic element that generates a synchronization character used in a serial data transmission protocol upon detection ...
06/20/2006
7065074Generalized divide-and-conquer networks
A generalized divide-and-conquer network and concomitant methodology for recursively constructing large-scaled switching fabrics to meet the need for present-day broadband switching. Such a network achieves optimal layout complexity among the class of banyan-type ne...
06/20/2006
7065076Modular scalable switching networks
An embodiment of the present invention is disclosed to include a three stage scalable switching network that can be built from a common module. Further disclosed are methods for building switching network v(k, n, m) from a common module comprising a (n×k) input swi...
06/20/2006
7035254Conditionally nonblocking switch of the upturned compressor type
Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is ...
04/25/2006
7031653Switch matrix for satellite payloads with multiple uplink beams and on-board signal processing
A method and apparatus for switching signals through a switch matrix are disclosed. The apparatus comprises an input module and an output module. The input module has a plurality of inputs typically equal to a number of cells in a reuse pattern, and the inputs recei...
04/18/2006
7020135Rearrangeable switch having a non-power of two number of physical center stages
A switch is provided that includes three stages. The first stages has a plurality of switch circuits. The second stage has a plurality of switch circuits equal to N, where N is any integer other than a power of 2 and where the switch circuits can be logically config...
03/28/2006
7017098Built-in self-test for multi-channel transceivers without data alignment
A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplary embodiment of ...
03/21/2006
7009964Rotator switch data path structures
Several rotator switch architectures are provided that enhance performance of a basic rotator switch. The rotator switches having double buffered tandem nodes, multiplexing two or more sources onto each tandem node, partitioning the rotator into two or more parallel...
03/07/2006
7003602Data bus
In apparatuses (1, 2, 3) controlled or operated via an I2 C bus, it may be necessary to take measures to suppress interference signals at the data signal input/output of the respective apparatus without impairing the data transport at the same time. The d...
02/21/2006
6999466Switching concentrator
An m-to-n concentrator constructed from smaller concentrator/sorters wherein m is not necessarily equal to 2n. For instance, the m-to-n concentrator can be implemented from an └m/2┘-to-n concentrator/sorter, an ┌m12┐-to-n concentrator/sorter, and n sorting c...
02/14/2006
6982975Packet switch realizing transmission with no packet delay
In a packet switch structured by connecting unit switches in multi-stages which is capable of transmitting packets without delay and accommodating high-speed lines, unit switches at the first stage assign, to an input packet, a sequence number according to a destina...
01/03/2006
6975626Switched network for low latency communication
A switched network includes a buffer-less switch coupling the sending nodes and the receiving nodes. The switch transmits packets successfully delivered to the receiving nodes through the buffer-less switch with a fixed forwarding rate. The switched network resolves...
12/13/2005
6941236Apparatus and methods for analyzing graphs
A plurality of hardware cells are defined, wherein at least a given one of the hardware cells corresponds to sets of vertices from a graph having vertices and edges interconnecting the vertices, and each of the sets are from a corresponding one of a number of portio...
09/06/2005
6885663Time/space switching component with multiple functionality
A time/space switching component is provided with multiple functionality that includes a time switching unit, of a space switching unit of a data channel sequence correction unit and of a control unit. As a result of corresponding mode selection, the different funct...
04/26/2005
6816486Cross-midplane switch topology
A chassis for holding modules including a set of first modules oriented horizontally in the chassis and a set of second modules oriented vertically in the chassis. A midplane is oriented orthogonally to the sets of first and second modules. The midplane has connecto...
11/09/2004
6714537Switch fabric architecture and techniques for implementing rapid hitless switchover
A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routing each frame ...
03/30/2004
6696917Folded Clos architecture switching
A novel folded Clos switch apparatus and method therefore for reducing the number of unemployed I/O terminals of a multistage Clos switching network by partitioning a crossbar switch to provide both the first (yth) and last (x-y+1th) stage of a multistage...
02/24/2004
6531953Method of controlling detouring in integrated network and communication device based on such method
A method of controlling detouring in an integrated network which includes communication devices includes the steps of registering routes at a communication device connected to terminal devices of respective media types such that the routes include a main ...
03/11/2003
6525650Electronic switching matrix
A high density electronic switching matrix (ESM) includes several splitting modules (200) arranged along a first axis, each including a signal input (202) and several splitter outputs (204). The ESM (500, 600) further includes several switching modules (4...
02/25/2003
6430179Three stage router for broadcast application
A multi-stage signal router includes a clocked storage element connected to each output of each stage of the router. Each clocked storage element is responsive to a trigger event of a clock signal to capture a signal level present at the output to which i...
08/06/2002
6343075Rearrangeable switch having a non-power of two number of physical center stages
A switch is provided that includes three stages. The first stages has a plurality of switch circuits. The second stage has a plurality of switch circuits equal to N, where N is any integer other than a power of 2 and where the switch circuits can be logic...
01/29/2002
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