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| Number | Title | Issue Date |
| 7825777 | Packet processors having comparators therein that determine non-strict inequalities between applied operands An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a firs... | 11/02/2010 |
| 7561023 | Comparing counter contents for timing critical applications An electrical circuit for comparing contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circ... | 07/14/2009 |
| 7437402 | Low-power, high-speed word comparator Apparatus and method for performing a high-speed, low-power bit-wise comparison of two digital words. For each bit, a bit comparator is shown, employing a compare node and a discharge node. After both nodes are charged, the discharge node is discharged and the condi... | 10/14/2008 |
| 7395303 | Method and device for comparing binary data words A system and method for comparing binary data words are provided, which method includes splitting a first and a second data word (A, B) to be compared to one another into at least two subwords, one having high-order bits (hA, hB) and the other having low-order bits ... | 07/01/2008 |
| 7388470 | Comparator having small size and improved operating speed A comparator having a small number of logic circuits and an improved operating speed is provided, where the comparator includes m number of bit comparators, each connected between a first node and a second node, comparing each corresponding bit between the first dat... | 06/17/2008 |
| 7382230 | Comparing counter contents for timing critical applications An electrical circuit and method to compare contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip f... | 06/03/2008 |
| 7379041 | Interface and method for error detection in image data transmission An interface and a method for image data transmission that is used for data transmission through a plurality of data lines is described, the correctness of the transmitted data being checked by reference to control data. The checking capability is achieved in that a... | 05/27/2008 |
| 7374006 | Method and device for determining the roadway condition A method and a device for determining the condition of roadway surfaces includes transmitting electromagnetic radiation at at least two different frequencies in the GHz range, reflecting and/or scattering the electromagnetic radiation by the roadway surface and subs... | 05/20/2008 |
| 7370120 | Method and system for reducing network latency in data communication Methods and systems for accelerating data communication by reducing network latency particularly by data compression in which requested data is recursively compressed by an encoder and sent to the requester in codes which may or may not be understood by the requeste... | 05/06/2008 |
| 7362248 | Temperature tamper detection circuit and method A sensing circuit determines whether an integrated circuit is currently exposed to one of a relatively low or a relatively high temperature. A selection circuit selects a measured voltage across the base-emitter of a bipolar transistor if the sensing circuit indicat... | 04/22/2008 |
| 7352275 | Device for comparing two words of n bits each The disclosure relates to a device for comparing two words, N and P, of n bits each. The device includes at least one comparator block comprising n basic comparator blocks which can each be used to compare bits Ni and Pi of digit place i of words N and P, whereby 0=... | 04/01/2008 |
| 7332939 | Comparator system and method for comparing an input signal with a reference level using said system A comparator system for comparing a level of an input signal with a level of a reference signal comprises a first comparator configured to input the input signal to one of input terminals thereof and the reference signal to the other of input terminals thereof, a se... | 02/19/2008 |
| 7330126 | Power supply controller A power supply controller is used in a device including at least one component and at least one control board for controlling an operation of each component, and includes: a power supply section; and a power supply board for independently supplying a power supply vo... | 02/12/2008 |
| 7315964 | Digital signal measuring apparatus and traffic observing method A digital signal measuring apparatus comprises a bus probe unit for extracting a bus event occurring on a bus based on a digital bus signal on the bus of the system to be measured, a traffic measuring unit for counting the number of occurrences of bus event based on... | 01/01/2008 |
| 7295199 | Matrix display having addressable display elements and methods A display device including a plurality of display elements (500) arranged in a matrix, wherein each display element includes a display pixel (510) coupled to a switch (530), and each display element includes an addressable latch (540) hav... | 11/13/2007 |
| 7292249 | Appropriately rendering a graphical object when a corresponding outline has excessive control points The principles of the present invention relate to appropriately rendering a graphical object when a corresponding outline has excessive control points. A computer system identifies a point of junction between a first and second feature of the outline. The computer s... | 11/06/2007 |
| 7283038 | Comparing counter contents for timing critical applications An electrical circuit and method to compare contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit. The first counter circuit is for re... | 10/16/2007 |
| 7284028 | Comparator eliminating need for one's complement logic for signed numbers An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag genera... | 10/16/2007 |
| 7271703 | 2-bit binary comparator and binary comparing device using the same A 2-bit binary comparator, including: a comparison unit for receiving a first bit and a second bit to thereby compare the first bit with the second bit; and an enable unit for outputting a comparison result of the comparison unit as an output of the 2-bit binary com... | 09/18/2007 |
| 7263563 | Multi-bus driver apparatus and method for driving a plurality of buses A bus driving method and apparatus for driving a plurality of buses including a control logic for generating and outputting control signals and bus selection signals, a byte rotator for dividing data from a data source into a data unit, and changing a sequence of th... | 08/28/2007 |
| 7260593 | Device for determining the rank of a sample, an apparatus for determining the rank of a plurality of samples, and the irank ordered filter A rank-determining device determines the rank of a particular sample value from a set of digital sample values by utilizing two different thresholders that are implemented by comparators. The rank of the sample value is decomposed by thresholding the sample value wi... | 08/21/2007 |
| 7256786 | Appropriately rendering a graphical object when a corresponding outline has exact or inexact control points The principles of the present invention relate to appropriately rendering a graphical object when a corresponding outline has exact or inexact control points. Based on the positions of control points on an outline it is calculated, that between a first parent contro... | 08/14/2007 |
| 7242630 | Memory device with reduced leakage current A technique for reducing the bitline leakage current while maintaining a level of performance characteristics of low threshold voltage transistors in deep submicron CMOS technology incorporates a reference voltage generator circuit in combination with bias transisto... | 07/10/2007 |
| 7233964 | Method and system for compositing three-dimensional graphics images using associative decision mechanism A method and system for compositing a plurality of three-dimensional Sub-Images by examining the Depth values of the Pixels corresponding to same spatial location in each Sub-Image and compositing the content of the Pixel having the greatest Depth value. The Depth v... | 06/19/2007 |
| 7233179 | Output stage interface circuit for outputting digital data onto a data bus An output stage interface circuit (1) comprises a main bipolar transistor (Q1) coupling a data output terminal (5) to a first rail (2) to which the positive of the power supply voltage (VDD) is applied, and a substrate diffusio... | 06/19/2007 |
| 7228248 | Test apparatus, timing generator and program therefor There is provided a test apparatus including a PLL circuit for generating a strobe signal of which the timing is shifted according to a given delay control voltage, a variable delay circuit being provided divergently from a path connecting the PLL circuit and the ti... | 06/05/2007 |
| 7227766 | Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisi... | 06/05/2007 |
| 7222078 | Methods and systems for gathering information from units of a commodity across a network In an exemplary system, information is received at a central location from different units of a commodity. The information is generated from two-way local interactions between users of the different units of the commodity and a user interface in the different units ... | 05/22/2007 |
| 7219280 | Integrated circuit with test signal routing module Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks and a routing module. The routing module is configured to receive test input vectors, select at least one logic block, select a routi... | 05/15/2007 |
| 7218686 | Decision threshold voltage control circuit and decision threshold voltage controlling method of clock and data recovery circuit, optical receiver, and decision threshold voltage control program According to a decision threshold voltage controlling method of feeding an optimum decision threshold voltage to a clock and data recovery circuit which converts an optical input signal into an electric signal, extracts a clock component from an input data signal am... | 05/15/2007 |
| 7210078 | Error bit method and circuitry for oscillation-based characterization A method for evaluating an output of a sequential circuit 2 by storing a series of output pulses from the sequential circuit 2 and determining whether the output pulses 4 toggled as desired. Also a circuit 1 for evaluating an output 4 | 04/24/2007 |
| 7206920 | Min/max value validation by repeated parallel comparison of the value with multiple elements of a set of data elements A method of locating a target value includes loading the target value into elements of a first register. The first register includes N elements (N>0). The method also includes indicating in elements of a second register, which includes N elements corresponding to th... | 04/17/2007 |
| 7200735 | High-performance hybrid processor with configurable execution units A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and... | 04/03/2007 |
| 7191895 | Conveyor induct system with probability estimator A conveyor system, such as an induction subsystem for supplying articles to a sortation subsystem, and method of conveying articles includes providing a conveying surface for conveying a series of articles and at least one sensor for sensing the articles on the conv... | 03/20/2007 |
| 7193505 | Channel-to-channel compare A word recognizer for providing a channel-to-channel compare for an input digital signal divides channels of the input digital signal into equal-width input signal channel paths. One input signal channel path serves as a reference value for comparison with the other... | 03/20/2007 |
| 7185253 | Compacting circuit responses Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrat... | 02/27/2007 |
| 7162713 | Difference engine method and apparatus A method and apparatus for analyzing and formatting strings of data, such as data derived from software processes running on two data processors. In one embodiment, a plurality of different data strings are initialized building a symbol array, and finding difference... | 01/09/2007 |
| 7154327 | Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory system A write counter provides a write count value synchronized with a write clock signal. A read counter provides a read count value synchronized with a read clock signal. The read and write count values are routed through logic, which introduces noise to these values. A... | 12/26/2006 |
| 7149938 | Non-causal channel equalization A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing three thresholds; receiving a binary serial data stream; comparing the first bit estimate in the data stream to a second bit value rec... | 12/12/2006 |
| 7137046 | High speed comparator for 10G SERDES An error counter including receive logic to compare transmitted bits with received bits and output a vector with a logic 1 for every bit that does not match and a logic 0 for every bit that matches. A plurality of stages are sequentially arranged. Each stage include... | 11/14/2006 |
