"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 7274283 | Method and apparatus for resisting hardware hacking through internal register interface Methods and apparatus that allow restricted access to internal registers of an integrated circuit (IC) device via an interface are provided. Unrestricted access to internal registers via the interface may be allowed during a manufacturing process to allow device tes... | 09/25/2007 |
| 5598343 | Method of segmenting an FPGA channel architecture for maximum routability and performance The current invention considers automatic synthesis of segmented channel architecture of row-based FPGAs so as to achieve maximum routability and performance. The routability of a channel and the performance of the routed nets may have conflicting require... | 01/28/1997 |
| 5027315 | Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions The present invention provides an output logic macrocell for controlling configuration of an output for an integrated circuit wich provides a logic signal including a register responsive to a clock signal for latching the logic signal to provide a registe... | 06/25/1991 |
| 4852044 | Programmable data security circuit for programmable logic device An architecture security fuse circuit is disclosed for securing the architecture of a configurable programmable logic device. The storage element of the circuit is a floating gate transistor cell. Data stored in the cell is determined by the amount of cha... | 07/25/1989 |
| 4670748 | Programmable chip select decoder Programmable chip select decoder including a higher level of integration such that the entire chip select decoder circuitry is provided on a single integrated circuit to avoid the problems previously associated with multi-chip approaches. The CMOS impleme... | 06/02/1987 |
| 3974366 | Integrated, programmable logic arrangement An integrated, programmable logic arrangement includes an AND matrix and an OR matrix which have individual gates. In the AND matrix each input is connected to a control line and via an inverter to another control line for production of a complementary in... | 08/10/1976 |