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| Number | Title | Issue Date |
| 7116229 | Programming a remote control device using RFID technology A system for programming a remote control device incorporates a battery-powered radio frequency identification (RFID) reader into the remote control device. A passive RFID transponder is embedded into the electronic consumer device, or is otherwise provided to the c... | 10/03/2006 |
| 7064675 | Context-sensitive remote controls Subject matter includes a reprogrammer for roving remote controllers that are capable of being used in multiple locations with different devices to be controlled at each location. An exemplary roving remote controller changes control code sets to operate whatever de... | 06/20/2006 |
| 6567133 | Method and apparatus for selecting an option in a system An option is selected from a plurality of options by selecting a soft key from a plurality of displayed soft keys, each corresponding with a respective one of the options. The soft keys are displayed as a number of distinguishable groups of soft keys. A u... | 05/20/2003 |
| 6292923 | Configurable interface module A configurable interface module particularly suited for processing of digital and analog information includes at least one field programmable gate array (44, 46, 48) mounted on a mezzanine board (30) to provide functional flexibility and not requiring an ... | 09/18/2001 |
| 6289496 | Placement of input-output design objects into a programmable gate array supporting multiple voltage standards A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites arranged into banks supporting interfaces with a plurality of... | 09/11/2001 |
| 6243664 | Methods for maximizing routability in a programmable interconnect matrix having less than full connectability Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width wmux that is less than number of input c... | 06/05/2001 |
| 6205574 | Method and system for generating a programming bitstream including identification bits A method and system for generating a programming bitstream for a programmable gate array. A programming bitstream for the programmable gate array is generated in response to an input design specification. The programming bitstream includes one or more unu... | 03/20/2001 |
| 6113260 | Configurable interface module A configurable interface module particularly suited for processing of digital and analog information includes at least one field programmable gate array (44, 46, 48) mounted on a mezzanine board (30) to provide functional flexibility and not requiring an ... | 09/05/2000 |
| 5760603 | High speed PLD "AND" array with separate nonvolatile memory The invention is a unique high speed Programmable Logic Device ("PLD") AND array with separate nonvolatile memory. The invention utilizes a separate nonvolatile memory to isolate the effect of nonvolatile transistors from the proper operation of the PLD A... | 06/02/1998 |
| 5760605 | Programmable high speed routing switch A programmable high speed routing switch is provided which has a lower ON-resistance so as to increase its gate oxide reliability. The routing switch includes a non-volatile memory cell (12) having a floating gate (FG). The floating gate is selectively ch... | 06/02/1998 |
| 5687325 | Application specific field programmable gate array An application specific field programmable gate array ("ASFPGA") includes at least two fixed functional units in a single IC chip. Depending upon a specific application for the ASFPGA, the fixed functional units may include one or more bus interfaces, eve... | 11/11/1997 |
| 5608649 | Directly programmable networks A procedure for establishing a scalable spanning tree over a network composed of nodes and links in which the resources for each node is independent of the size of the network. The procedure involves the selection of a set of states, a set of messages, st... | 03/04/1997 |
| 5598346 | Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes ... | 01/28/1997 |
| 5587921 | Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes ... | 12/24/1996 |
| 5586044 | Array of configurable logic blocks including cascadable lookup tables A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes ... | 12/17/1996 |
| 5341044 | Flexible configuration logic array block for programmable logic devices A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic sign... | 08/23/1994 |
| 5319361 | Circuit managing numbers of accesses to logic resources A circuit managing numbers of accesses to logic resources, such as buffer memory data cells in a time switching system. The circuit is structured around a counting cell matrix including a synchronous counter storing an instananeous number of accesses rela... | 06/07/1994 |
| 5317698 | FPGA architecture including direct logic function circuit to I/O interconnections A user-programmable FPGA architecture includes a plurality of logic function circuits including inputs and outputs disposed on an integrated circuit. A plurality of input/output (I/O) modules are also disposed on the integrated circuit and each include an... | 05/31/1994 |
| 5253363 | Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential local array A universal sequential logic circuit is constructed from a rectilinear array of elementary logic "cells", with a relatively large number of logic states embodied in a relatively small array. The set of states from a state-machine description of the logic ... | 10/12/1993 |
| 5233539 | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes dire... | 08/03/1993 |
| 5231588 | Programmable gate array with logic cells having symmetrical input/output structures A configurable logic array includes an array of configurable logic cells arranged in columns and rows. A plurality of input/output cells are arranged around the perimeter of the array, and provide interfaces to input/output pads on the chip. A configurabl... | 07/27/1993 |
| 5212652 | Programmable gate array with improved interconnect structure A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes dire... | 05/18/1993 |
| 5191325 | Programmable relay control device A programmable relay control device is provided for determining the level of at least two outputs as a function of signals present at the inputs and timing signals from a clock, comprising down-counting decades and programming and reprogramming means. Thi... | 03/02/1993 |
| 5015885 | Reconfigurable programmable interconnect architecture A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring chan... | 05/14/1991 |
| 5003200 | Programmable logic device having programmable wiring for connecting adjacent programmable logic elements through a single switch station There is provided a programmable logic device (PLD) which includes a programmable wiring, the programmable wiring comprising: a plurality of switch stations (SS), first wirings each for directly connecting some terminals among input/output terminals of sa... | 03/26/1991 |
| 4959646 | Dynamic PLA timing circuit A dynamic PLA timing circuit in a PLA ROM includes a first PLA line and the address section only of another PLA line. The address section of the first PLA line is connected to the true address lines and the address section of the other PLA line is connect... | 09/25/1990 |
| 4931671 | Multiple array customizable logic device Disclosed is an integrated circuit having multiple programmable arrays providing customizable logic. The integrated circuit has at least a first programmable array receiving a plurality of first inputs and generating a plurality of first outputs as progra... | 06/05/1990 |
| 4924440 | MOS gate array devices A MOS gate array has a PLA formed in a memory area which includes a plurality of first and second elementary unit circuits. The first elementary unit circuit includes two output lines, one input line, two PMOS transistors, and four NMOS transistors. The s... | 05/08/1990 |
| 4920515 | Programmable logic array having an improved testing arrangement A programmable logic array (PLA) whose AC characteristics such as an input-to-output delay characteristic can be measured includes a plurality of input lines, a plurality of product term lines, a plurality of non-volatile memory elements, and a test input... | 04/24/1990 |
| 4896296 | Programmable logic device configurable input/output cell An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and henc... | 01/23/1990 |
| 4866309 | Multiplexed bus architecture for configuration sensing The invention provides a circuit for use with a standard bidirectional databus having an active current device providing a first logic level in combination with a selectably jumpered passive resistance device providing a second logic level, the active ele... | 09/12/1989 |
| 4845633 | System for programming graphically a programmable, asynchronous logic cell and array A system for programming an asynchronous logic cell and a two- or three-dimensional array formed of such cells. Each cell comprises a number of exclusive-OR gates, Muller C-elements and programmable switches. The logic cell is reprogrammable and may even ... | 07/04/1989 |
| 4841174 | CMOS circuit with racefree single clock dynamic logic Disclosed is an improved logic circuit employing dynamic CMOS logic and having alternating logic employing first and second conductivity type transistors, respectively, separated by clocked inverters. The circuit employs a single clock signal to synchroni... | 06/20/1989 |
| 4815036 | Programmable logic array having an on/off sense function A programmable logic array includes a plurality of semiconductor memory elements, such as FAMOSs, arranged in the form of an array and a sense circuit for receiving data out from the memory elements during read out mode. The present programmable logic arr... | 03/21/1989 |
| 4812685 | Dynamic logic array with isolation and latching means between planes A dynamic logic array circuit can operate in two clock phases. It includes two matrices (1, 2) comprising dynamic logical gates, which require a precharging phase that precedes a functional phase. The array also includes memorizing means (7), the inputs o... | 03/14/1989 |
| 4797746 | Digital image interface system A digital image interface system converts digital image information from a first format to a second format. The interface system includes a data input line for receiving input data, which may include a plurality of frames and fields of digital image infor... | 01/10/1989 |
| 4771284 | Logic array with programmable element output generation A programmable logic array having a plurality of electrically isolated input lines connected to an input circuit for providing an input signal to one of the plurality of input lines. Also included are a plurality of electrically isolated output lines posi... | 09/13/1988 |
| 4771282 | Terminal for data transmission system A terminal device for a multiplexed data transmission system has a decoder matrix having plural groups of function setting inputs for selecting plural types of functions such as interface, operation modes and other. One group of the function setting input... | 09/13/1988 |
| 4766569 | Programmable logic array A programmable logic array is disclosed employing arrays of electrically erasable and programmable cells. The device includes a dual purpose programming circuit which is employed to provide programming data to the AND array to program the AND array cells,... | 08/23/1988 |
| 4740721 | Programmable logic array with single clock dynamic logic Disclosed is a programmable logic array employing dynamic CMOS logic and utilizing a single clock signal and its complement to synchronize said dynamic logic operations. The PLA disclosed employs two logic planes for implementing arbitrary logic equations... | 04/26/1988 |
