Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 7312645 | Adaptive transition density data triggered PLL (phase locked loop) Adaptive transition density data triggered PLL (Phase Locked Loop). A novel solution is presented within a data triggered PLL whereby the missing data edge transitions may be detected and used to modify a phase difference between a data signal and a feedback signal ... | 12/25/2007 |
| 7266169 | Phase interpolater and applications thereof A phase interpolator includes a plurality of clock phase input sections, a plurality of clock phase switching sections, a plurality of current sources and a load. Each of the clock phase input sections is coupled to receive one of a plurality of reference clock phas... | 09/04/2007 |
| 7239651 | Desynchronizer having ram based shared digital phase locked loops and sonet high density demapper incorporating same A SONET demapper includes three desynchronizers, each of which includes a RAM-based, shared digital phase locked loop, shared elastic storage, and twenty-eight divide-by 33/34/44/45 counters. Unlike a conventional desynchronizer which uses separate FIFOs for each of... | 07/03/2007 |
| 7161391 | Skew tolerant high-speed digital phase detector A skew-tolerant digital phase detector is provided. Specifically, a detector is provided in the digital phase detector to detect certain failure conditions that may result from clock skew and duty cycle distortion. If the condition is detected, an adjusted signal is... | 01/09/2007 |
| 7123069 | Latch or phase detector device The invention relates to a circuit device, into which a first signal and a second signal are input, wherein a first switching array is provided, by means of which it is determined which of the two signals, is the first to change its state. The circuit device may als... | 10/17/2006 |
| 7039148 | Phase detector and signal locking system controller A phase detector and signal locking system controller for use in a digital phase-locked loop (PLL) application includes a first and a second phase detector where the first phase detector result is used to control the initial pull-in and the second phase detector is ... | 05/02/2006 |
| 6959317 | Method and apparatus for increasing processing performance of pipelined averaging filters A pipelined processor such as an averaging filter including at least one subtractor section and at least one adder section. Both of the subtractor section and the adder section have a plurality of adder logic units. In comparison to the conventional processor, the p... | 10/25/2005 |
| 6959063 | Fractional-N phase locked loop A phase-locked loop has a phase detector that generates a phase difference signal, a circuit that generates a phase-locked loop output signal having a frequency that is a function of the phase difference signal, a frequency divider that receives the phase-locked loo... | 10/25/2005 |
| 6955539 | Characterization of motion of dual motor oral hygiene device An oral hygiene device is disclosed having at least two motors to simultaneously vibrate and impart motion upon the head portion of the oral hygiene device, most beneficially at the tip. A first motor is positioned in the handle portion of the device to impart a fir... | 10/18/2005 |
| 6856207 | Jitter-less phase detector in a clock recovery circuit A jitter-less phase detector in a clock recovery circuit is disclosed. A first control signal generating circuit generates a first control signal by inverting and delaying input data signals through half clock. A second control signal generating circuit generates a ... | 02/15/2005 |
| 6791906 | Method and system for fail-safe control of a frequency synthesizer In a preferred embodiment, the invention provides a method and system for allowing a frequency synthesizer to function despite long delays. A first and second phase comparator, each with at least three inputs and an output are preset to a predetermined logical value... | 09/14/2004 |
| 6496077 | Phase detector for automatically controlling offset current and phase locked loop including the same A phase detector includes a Gilbert block for outputting a signal proportional to a phase difference between first and second input signals to a first output terminal, and a current source for determining a current in the first output terminal. The curren... | 12/17/2002 |
| 6362693 | Frequency detection method for adjusting a clock signal frequency and a frequency detector circuit for carrying out the method In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided b... | 03/26/2002 |
| 6333679 | Phase locked loop arrangement in which VCO frequency is a fraction of reference frequency In a phase locked loop arrangement of a frequency synthesiser, a signal outputted from a voltage controlled oscillator is locked to a reference oscillator. A phase detector is arranged so that the frequency of the reference oscillator is a multiple of the... | 12/25/2001 |
| 6278330 | Frequency and phase offset signal generator and method A signal generator and a method of generating a signal are disclosed that offsets phase and frequency of the output signal relative to the input signal by small increments, providing high resolution. The signal generator utilizes numerically controlled os... | 08/21/2001 |
| 6255911 | PLL circuit protected against noise and missing pulses in a reference signal A PLL circuit used in an apparat as for reading and writing data to a disk compensates for noise which causes a false clock signal or for missing clock signals which can be caused by a scratch or smudge on the surface of the disc. The PLL circuit includes... | 07/03/2001 |
| 6121846 | Digital phase comparator without dead zone A digital phase comparator comprises a first signal input (VCO) and second signal input (REF) as well as a first output (UP+) and second output (DOWN+). It is arranged so as to produce an output pulse (503, 504) to the first output and second output per e... | 09/19/2000 |
| 6094101 | Direct digital frequency synthesis enabling spur elimination The present invention, generally speaking, provides improved methods of generating clean, precisely-modulated waveforms, at least partly using digital techniques. In accordance with one aspect of the invention, a "difference engine" is provided that produ... | 07/25/2000 |
| 6075415 | Digital frequency multiplier A digital frequency multiplier is provided that continues to adjust its multiplied frequency after the desired multiplied frequency is reached, that can be tested during operation and that is easily scalable. The digital frequency multiplier comprises a f... | 06/13/2000 |
| 6060953 | PLL response time accelerating system using a frequency detector counter A PLL response time is accelerated with a frequency detector counter. The PLL utilizes both a phase frequency detector and the frequency detector counter. Initially, the operation of the PLL is controlled by the frequency detector counter and the output o... | 05/09/2000 |
| 6054904 | Voltage controlled ring oscillator and charge pump circuit A voltage controlled ring oscillator has a current control circuit and an odd number of inverter circuits. Each inverter circuit has a current charge preventing circuit connected between a ground voltage and a connection node located between a current sou... | 04/25/2000 |
| 6046644 | Phase-locked loop oscillator formed entirely of logic circuits Phase-locked loop oscillators that are designed to set the clock rate of electronic circuits based on combinations of logic circuits and to be integrated, at the same time as these electronic circuits, into one and the same chip. There is proposed a phase... | 04/04/2000 |
| 5936472 | Oscillating circuit with limitation function of oscillation frequency In an oscillating circuit, an oscillator generates an oscillation signal with a frequency, increases the frequency of the oscillation signal in response to a frequency increase signal and decreases the frequency of the oscillation signal in response to a ... | 08/10/1999 |
| 5889437 | Frequency synthesizer with low jitter noise An improved apparatus for combining frequencies which is capable of generating a constant frequency when an external variation is applied thereto by implementing each block using a differential circuit, whereby it is adaptable to a mobile communication sy... | 03/30/1999 |
| 5880642 | Programmable frequency synthesizer having a low sensitivity to phase noise A frequency synthesizer SYNT intended to supply an output signal Sout having an output frequency which depends on the average frequency, referred to as symbol frequency, of an input signal Sin beset with a strong phase noise. This synthesizer SYNT include... | 03/09/1999 |
| 5847582 | Apparatus and method for producing symmetric capture range in two-quadrant phase detector PLLs using nonsymmetric pulse waves A symmetric capture range is produced in a two-quadrant phase detector phase locked loop that utilizes nonsymmetric pulse waves. The phase detector is enabled only during VCO pulses. A latch stores the relative relationship between the leading edge of the... | 12/08/1998 |
| 5841324 | Charge-based frequency locked loop and method A frequency locked loop (FLL) having an oscillator whose output frequency controls the amount of charge provided by a switched feedback capacitor to a charge integrator whose output voltage controls the frequency of the oscillator. A switched reference ca... | 11/24/1998 |
| 5770976 | Local clock duty cycle independent phase detector and method of operation thereof A phase detector for a phase-locked loop ("PLL") circuit under control of a local oscillating clock ("LOSC") signal and a method of operation thereof. The phase detector includes: (1) a first circuit that receives a reference data ("REF") signal and the L... | 06/23/1998 |
| 5754607 | Method and apparatus for achieving fast phase settling in a phase locked loop A method and an apparatus are provided to achieve fast phase settling when a reference signal for a phase locked loop changes from a first frequency to a second frequency, such as during holdover recovery in a synchronous optical network. The present meth... | 05/19/1998 |
| 5748043 | Digital PLL frequency synthesizer A digital frequency synthesizer includes a digital-to-analog (1), a low pass filter (2), and a controllable oscillator (3), where the oscillator output is the synthesizer output. K number of RS flip-flops (101-108) produce error signals which are coupled ... | 05/05/1998 |
| 5663685 | Dual flip-flop detector type phase locked loop incorporating dynamic phase offset correction Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop, which phase offset is due to circuit delays in the phase detector. Simultaneous "pump up" and "pump do... | 09/02/1997 |
| 5659268 | Dual flip-flop detector type phase locked loop incorporating static phase offset correction Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop. The phase offset is due to circuit delays in the phase detector which result in the issuance of simult... | 08/19/1997 |
| 5654674 | Oscillator control circuit with phase detection feedback A controllable crystal oscillator of a receiver having a mixer producing an IF signal is controlled by a feedback loop that includes a phase detector. The IF signal is delayed by an odd multiple of π/2 and fed to one input of an exclusive-OR circuit, wit... | 08/05/1997 |
| 5619171 | Phase-locked loop, phase comparator for use in the phase-locked loop, and reproducing device including the phase-locked loop A phase-locked loop includes an input terminal (1) for receiving a binary signal, a phase comparator (3) having a first input (2) coupled to the input terminal (1), having a second input (4), and having an output (5) coupled to an input (9) of a control-s... | 04/08/1997 |
| 5602512 | Comparator of phase between a digital signal and a clock signal, and corresponding phase locked loop A comparator of phase between a digital signal and a clock signal adapted for the construction of a phase locked loop in integrated circuit form, that includes a first channel formed by a flip-flop and an exclusive OR gate, and a second channel formed by ... | 02/11/1997 |
| 5592113 | Gradual frequency changing circuit An error-limiting circuit for regulating the time required to bring the output signal of a control system such as a phase-locked loop device into conformance with a reference input signal. For a phase-locked loop system the error-limiting circuit is a pha... | 01/07/1997 |
| 5589801 | Phase comparator circuit and phase synchronization circuit A phase comparator circuit in which an output synchronized with the input signal may be accurately produced without producing a malfunction even in the absence of the synchronization signal, in which a detection unit 11 detects the phase information of an... | 12/31/1996 |
| 5576664 | Discrete time digital phase locked loop A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accum... | 11/19/1996 |
| 5546052 | Phase locked loop circuit with phase/frequency detector which eliminates dead zones A phase locked loop circuit is provided which includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which do not have "dead zones". A pair of charge pumps receives the I... | 08/13/1996 |
| 5497127 | Wide frequency range CMOS relaxation oscillator with variable hysteresis A voltage controlled oscillator (VCO) which may be adjusted to provide oscillatory signals for a wide range of frequencies includes a relaxation oscillator in which a ramp signal is compared to a reference threshold which exhibits hysteresis. The frequenc... | 03/05/1996 |
