Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 8188795 | Phase comparator and reproduction signal processor using the same In a synchronous reproduction signal processor, when a phase error between reproduction data and a clock is repeatedly detected such that a clock synchronized with a reproduction signal is generated based on the phase error, a filtering process unit (34) perf... | 05/29/2012 |
| 8164390 | Regulating an operating condition of an integrated circuit to compensate for a manufacturing variation An integrated circuit has operational circuitry to perform an operation. An operational regulator regulates an operating condition of the operational circuitry. The operational regulator has a sample clock to generate a sample clock signal. The sample clock signal c... | 04/24/2012 |
| 8154351 | Voltage-controlled oscillator and gain calibration technique for two-point modulation in a phase-locked loop A VCO in a phase-locked loop (PLL) is arranged to receive low-pass data via a first input and high-pass data at a second input. The first input is coupled to a first set of varactors in the VCO. The second input is coupled to a second set of varactors in the VCO. Th... | 04/10/2012 |
| 8022775 | Systems and methods for maintaining a drive signal to a resonant circuit at a resonant frequency Systems and methods for maintaining a drive signal to a resonant circuit at a resonant frequency are provided. A system for maintaining a drive signal to a resonant circuit at a resonant frequency can include: an oscillator configured to provide an output to a phase... | 09/20/2011 |
| 7956696 | Techniques for generating fractional clock signals A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock sign... | 06/07/2011 |
| 7893775 | Frequency diverse discrete-time phase-lock device and apparatus A discrete-time phase lock loop (DTPLL) includes an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC. The DTPLL also includes a digital signal processor (DSP). The DSP... | 02/22/2011 |
| 7876164 | Phase locked oscillator There is provided an analog phase locked oscillator comprising a sampling phase detector, a loop filter, a voltage controlled oscillator, a frequency multiplier and a feedback loop where the feedback loop connects the output of said oscillator with the input of said... | 01/25/2011 |
| 7847641 | Digital phase and frequency detector Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a p... | 12/07/2010 |
| 7839222 | Systems and methods using programmable fixed frequency digitally controlled oscillators for multirate low jitter frequency synthesis The disclosure provides systems and methods for programmable fixed frequency digitally controlled oscillators for multirate low jitter frequency synthesis. The present invention utilizes a digital control element, such as a complex programmable logic device (CPLD) o... | 11/23/2010 |
| 7825740 | Systems and methods for tracking communication parameters over a plurality of frequency bands In at least some embodiments, a communication system includes a receiver having a local oscillator (LO) for each of a plurality of frequency bands. Each LO is controlled by a separate phase-locked loop (PLL) that tracks carrier frequency offset (CFO) using a common ... | 11/02/2010 |
| 7812678 | Digital calibration techniques for segmented capacitor arrays An apparatus includes phase detection circuitry that generates control signals in response to an input clock signal and a feedback clock signal. The apparatus also includes a clock signal generation circuit that includes fine and coarse capacitors. The clock signal ... | 10/12/2010 |
| 7804369 | Integrated frequency calibration architecture In an exemplary embodiment, a free running VCO has two modes: a normal operating mode and a calibration mode. In the calibration mode, the free running VCO is phase lock looped with itself instead of a calibration VCO. Furthermore, in an exemplary embodiment, a tuni... | 09/28/2010 |
| 7791417 | Mixed-mode PLL A mixed-mode PLL is disclosed. The mixed-mode PLL comprises an analog phase correction path and a digital frequency correction path. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a d... | 09/07/2010 |
| 7760030 | Phase detection circuit and method thereof and clock recovery circuit and method thereof The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a da... | 07/20/2010 |
| 7746180 | Phase-locked loop circuit and data reproduction apparatus This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functi... | 06/29/2010 |
| 7724095 | Floating DC-offset circuit for phase detector A floating DC-offset circuit for a phase detector. The circuit may provide a floating DC-offset to the phase detector, or to the voltage-controlled oscillator of the phase-locked loop. The circuit includes a voltage comparator, clock, digital resistor, and offset li... | 05/25/2010 |
| 7719368 | Configurable reset circuit for a phase-locked loop A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by... | 05/18/2010 |
| 7701299 | Low phase noise PLL synthesizer A low phase noise PLL synthesizer is described in which an initial tuning mechanism uses a conventional divider loop to lock a VCO to a desired output frequency. Once initial lock is achieved, the divider loop is switched out of the circuit in favor of a low phase n... | 04/20/2010 |
| 7692501 | Phase/frequency detector and charge pump architecture for referenceless clock and data recovery (CDR) applications A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at ... | 04/06/2010 |
| 7656237 | Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the u... | 02/02/2010 |
| 7639090 | Phase detector for reducing noise The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the dete... | 12/29/2009 |
| 7616069 | Method and system for fast PLL close-loop settling after open-loop VCO calibration Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop,... | 11/10/2009 |
| 7612619 | Phase detector device and method thereof A device and method for phase detection are disclosed. The device includes a phase differential module that provides a phase difference signal based on the phase difference between a data signal and a reference signal. The phase difference signal is provided to a fi... | 11/03/2009 |
| 7605667 | Frequency synthesizer with a harmonic locked phase/frequency detector A frequency synthesizer. The frequency synthesizer comprises a harmonic locked phase/frequency detector, a low pass filter, a voltage controlled oscillator, and a frequency divider. The harmonic locked phase/frequency detector receives a reference signal and a divid... | 10/20/2009 |
| 7592874 | Phase/frequency detector, phase locked loop, method for phase/frequency detection and method for generating an oscillator signal A phase/frequency detector has a modulo counter for outputting a counter word with a predetermined word length depending on an oscillator signal. In addition, a modulo integrator for outputting an integrator word with the predetermined word length as a function of i... | 09/22/2009 |
| 7583152 | Phase-locked loop with self-correcting phase-to-digital transfer function A phase-locked loop includes a phase-to-digital converter portion as well as a novel correction portion. The phase-to-digital converter (PDC) portion outputs a stream of first phase error words. The novel correction portion receives the first phase error words and g... | 09/01/2009 |
| 7564315 | System and method for pre-charged linear phase-frequency detector A method for comparing phases of two signals including placing a first output node in a floating state, detecting a first edge of a first signal on a first input node after placing the first output node in the floating state, coupling the first edge of the first sig... | 07/21/2009 |
| 7525393 | Digital frequency multiplier circuit A digital frequency multiplier circuit is disclosed. The digital frequency multiplier circuit includes a digitally controlled oscillator (DCO), a phase detector and a control circuit. The DCO generates an internal feedback signal. The phase detector detects a phase ... | 04/28/2009 |
| 7508277 | Phase-locked loop with VCO tuning sensitivity compensation The invention provides a phase-locked loop (PLL). Since a loop bandwidth of the PLL is a function of a gain of a phase detector and a gain of a voltage controlled oscillator (VCO), by adjusting the gain of the phase detector, the variation of the gain of the VCO (i.... | 03/24/2009 |
| 7501902 | Phase-locked loop circuit and data reproduction apparatus This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functi... | 03/10/2009 |
| 7489203 | Noise tolerant phase locked loop An apparatus and method for providing timing recovery under conditions of low signal to noise ratios (SNRs) is disclosed herein. A preliminary phase error signal is generated by comparing an input signal with a preliminary estimation of an output signal correspondin... | 02/10/2009 |
| 7463099 | Phase detector for reducing noise The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the dete... | 12/09/2008 |
| 7463100 | Phase frequency detector capable of improving noise characteristics A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO)... | 12/09/2008 |
| 7443250 | Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit... | 10/28/2008 |
| 7443251 | Digital phase and frequency detector Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a p... | 10/28/2008 |
| 7439812 | Auto-ranging phase-locked loop A phase locked loop circuit includes an oscillator, a dividing circuit coupled to the oscillator having a controllable dividing factor, and a rangefinder circuit coupled to the dividing circuit. The rangefinder circuit is configured to control the dividing factor in... | 10/21/2008 |
| 7440518 | Phase-locked loop circuit A PLL circuit comprises a controller (DRC) adjusting the frequency of frequency modulated signals (uDIV) provided by a frequency modulator (DIV) on the basis of signals provided by a linear range detector (LRD) so that the phase detector gets back into a ... | 10/21/2008 |
| 7436263 | Apparatus and method for presenting a modulated output signal at an output locus An apparatus that presents an output signal that is modulated by input signal includes: (a) A signal source providing a signal at a reference frequency. (b) A frequency comparer coupled with the signal source and the output signal for comparing the extant output sig... | 10/14/2008 |
| 7436265 | Clock generator and clock generating method using delay locked loop Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locke... | 10/14/2008 |
| 7432751 | High performance signal generation A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal ... | 10/07/2008 |
