Did You Know...
...that it was melting ice cream that inspired the invention of the outboard motor? It was a lovely August day and Ole Evinrude was rowing his boat to his favorite island picnic spot. As he rowed, he watched his ice cream melt and wished he had a faster way to get to the island. At that moment the idea for the outboard motor was born!
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| Number | Title | Issue Date |
| 8174324 | Digital phase detector, and digital phase locked loop including the same A digital phase detector includes a quantization unit that quantizes a frequency of a reference signal to generate reference delay information and reference integer phase information, and quantizes a frequency of an oscillation signal to generate oscillation delay i... | 05/08/2012 |
| 8143953 | Self-trim and self-test of on-chip values A self-trim circuit provides a technique to trim a CUT (circuit under trim) using a LSB offset to determine the best digital value to trim the CUT. The self-trim circuit is also used to self-test the digital and analog portions of the self-trim circuitry, whereby th... | 03/27/2012 |
| 8138840 | Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference c... | 03/20/2012 |
| 8134411 | Computation spreading utilizing dithering for spur reduction in a digital phase lock loop A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to... | 03/13/2012 |
| 8125278 | Clock regeneration apparatus and electric equipment Disclosed herein is a clock regeneration apparatus, including: an oscillator including n (an integer of two or more) gating groups connected in cascade connection to each other forming an oscillation loop, the gating groups being controlled to gate an internal clock... | 02/28/2012 |
| 8125277 | Dual loop frequency synthesizer A frequency synthesizer has a fractional N1 loop and an integer N2 loop. The output frequency of the signal of the fractional N1 loop is constrained to values between adjacent harmonics of a reference frequency used in the fractional... | 02/28/2012 |
| 8098103 | PLL disturbance cancellation Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more si... | 01/17/2012 |
| 8076978 | Circuit with noise shaper In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping. ... | 12/13/2011 |
| 8076977 | Device having digitally controlled oscillator A device includes a digitally controlled oscillator and an interpolator having a data input and a data output coupled to the digitally controlled oscillator. The interpolator may be configured to receive an oscillator control signal at the data input and to provide ... | 12/13/2011 |
| 8031007 | Error protection method, TDC module, CTDC module, all-digital phase-locked loop, and calibration method thereof An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADP... | 10/04/2011 |
| 7994866 | Auto trimming oscillator An auto trimming oscillator includes a Successive Approximation Register (SAR), a frequency detector and an n-bit comparator. The SAR is used to iteratively trim the oscillator output clock frequency based on a difference between a reference clock frequency and the ... | 08/09/2011 |
| 7994867 | Oscillator control apparatus An oscillator control apparatus has a digitally-controlled oscillator which outputs an oscillation signal having an oscillation frequency in response to an oscillator adjusting signal, a counter which counts the oscillation signal and outputs a count in response to ... | 08/09/2011 |
| 7990224 | Dual reference phase tracking phase-locked loop A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is configured to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector... | 08/02/2011 |
| 7986190 | Jitter attenuation with a fractional-N clock synthesizer A circuit, such as, but not limited to, a digital phase-locked loop (PLL) or a transport timing loop, uses a fractional-N modulator and a fractional-N clock synthesizer to generate a clock signal, such as a transmit clock signal, from a reference clock signal. One e... | 07/26/2011 |
| 7965143 | Digital phase detector and phase-locked loop A digital phase detector is provided that can be easily implemented in gate array or FPGA, to accurately quantize a phase difference of two clocks and convert to a digital value without using delay elements. The digital phase detector includes: a multiplier for, whe... | 06/21/2011 |
| 7956693 | Method and apparatus for adjusting PLL and/or DLL timing offsets A method and apparatus for adjusting PLL and/or DLL timing offsets have been disclosed. ... | 06/07/2011 |
| 7940127 | All digital phase lock loop and method for controlling phase lock loop An all digital phase lock loop is disclosed, including a digitally controlled oscillator, a phase detector, and a loop filter. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal. The oscillator tuning word in... | 05/10/2011 |
| 7936221 | Computation spreading for spur reduction in a digital phase lock loop A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially p... | 05/03/2011 |
| 7889012 | System and method for cycle slip prevention in a frequency synthesizer An improved method of cycle slip prevention in a frequency synthesizer is achieved by determining phase error between a divided VCO and reference, determining whether a phase error of a full cycle slip has occurred and in which direction and altering the phase of th... | 02/15/2011 |
| 7884674 | Clock and data recovery circuit An embodiment of the invention provides a clock and data recovery circuit. The clock and data recovery circuit comprises a phase detector, a pre-accumulator, a register, an accumulator and a digital controlled oscillator. By using the transmission path formed by the... | 02/08/2011 |
| 7859344 | PLL circuit with improved phase difference detection In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a T... | 12/28/2010 |
| 7859343 | High-resolution varactors, single-edge triggered digitally controlled oscillators, and all-digital phase-locked loops using the same A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to re... | 12/28/2010 |
| 7847639 | Pulse width modulation device A pulse width modulation device which a step form control signal generated by a control signal generating device and a triangular wavecarrier signal generated by a carrier generating device are compared by a digital comparator and the comparison signal is supplied t... | 12/07/2010 |
| 7843274 | Phase lock loop apparatus A phase lock loop apparatus is disclosed. The phase lock loop apparatus comprises a phase detecting module, a logic processing module, a charge pump and loop filter (CPLF), and a voltage control oscillator. The phase detecting module detects the phase difference bet... | 11/30/2010 |
| 7808325 | System and method for frequency pushing/pulling compensation A system and method for frequency pushing/pulling compensation in phase-locked loops including a method for cancelling frequency push/pull in an oscillator of a transmitter. The method includes computing an error signal from a signal of a phase locked loop, wherein ... | 10/05/2010 |
| 7791415 | Fractional-N synthesized chirp generator A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a refere... | 09/07/2010 |
| 7768355 | Polyphase numerically controlled oscillator A polyphase numerically controlled oscillator is disclosed. An input signal is received at a phase accumulator. The phase accumulator provides a phase to a phase interpolator. The phase interpolator then provides a plurality of output phases. The plurality of output... | 08/03/2010 |
| 7746177 | Self-biased bipolar ring-oscillator phase-locked loops with wide tuning range Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked loop is described, comprising a voltage-controlled oscillator (VCO) to provide an output clock signal havin... | 06/29/2010 |
| 7746178 | Digital offset phase-locked loop The present invention relates to a digital offset phase-locked loop (DOPLL), which may have advantages of size, simplicity, performance, design portability, or any combination thereof, compared to analog-based phase-locked loops (PLLs). The DOPLL may include a digit... | 06/29/2010 |
| 7741917 | Noise shaping time to digital converter According to an embodiment of a time to digital converter, the time difference between a signal of interest and a reference signal is measured by operating a digitally controlled oscillator at a first frequency during a first portion of the reference signal period a... | 06/22/2010 |
| 7737791 | Spread spectrum clocking in fractional-N PLL In applications that use fractional-N phase locked loops (PLLs), the use of spread spectrum clocking (SSC) to reduced electromagnetic interference (EMI) would be desirable, but conflicts can occur. Here, a circuit is provided that includes both fractional logic circ... | 06/15/2010 |
| 7724093 | Phase locked loop with two-step control A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (fOSC), a clock divider coupled to the DCO and receiving the DCO output signal and outputting a feedback clock signal (fN), and a phase frequency... | 05/25/2010 |
| 7710205 | Capacitor detection by phase shift A method and apparatus for detecting capacitive devices are disclosed. A circuit including two circuit paths is connected to an oscillator voltage source. Connecting a test capacitive device to a path of the circuit modifies the electric potential waveform at a poin... | 05/04/2010 |
| 7679453 | Phase-locked loop capable of dynamically adjusting phase of output signal according to detection result of phase/frequency detector, and method thereof A phase-locked method includes: generating a selection signal according to a detection result of a phase/frequency detector (PFD) of a phase-locked loop (PLL); generating a plurality of oscillation signals according to at least a first oscillation signal generated b... | 03/16/2010 |
| 7667544 | Clock reproducing apparatus A clock reproducing apparatus includes a clock reproducing circuit having: a gated oscillator having an oscillating circuit of two routes; and a frequency control circuit for comparing a phase of an output of the gated oscillator with a phase of a reference clock, a... | 02/23/2010 |
| 7656234 | Circuit and oscillating apparatus A circuit includes a logic circuit containing a first transistor and a second transistor which are connected in series to each other between a high power supply and a low power supply in such a manner that an emitter of one of the first and second transistors is con... | 02/02/2010 |
| 7652540 | Fine clock resolution digital phase locked loop apparatus A digital phase locked loop apparatus includes an input signal time detecting device that detects a phase of an input signal with prescribed time resolution obtained by dividing a cycle of an operation clock generated by a clock generator at a prescribed time. An ou... | 01/26/2010 |
| 7639086 | Thermometer code generator, and frequency-locked loop including the same A thermometer code generator includes n bit storing stages that are coupled to each other, where n is an integer greater than 1, and the n bit storing stages store a thermometer code, and are adapted to increase the stored thermometer code by 1 in synchronization wi... | 12/29/2009 |
| 7616063 | Frequency synthesizer using a phase-locked loop and single side band mixer A frequency synthesizer is built using a phase locked loop incorporating a single side band mixer either in the feedback loop or in the input. The single side band mixer is preferably realized with digital logic and FETs, and the resulting frequency synthesizer simu... | 11/10/2009 |
| 7616064 | Digital synthesizer for low power location receivers A high-frequency phase locked loop synthesizer having a selectable fractional-N divider and integer divider along with a phase frequency detector implemented as a CMOS logic block. ... | 11/10/2009 |
