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"Rail travel at high speeds is not possible because passengers, unable to breathe, would die of asphyxia."
Dionysius Lardner, Professor of Natural Philosophy and Astronomy at University College, London ; 1830
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| Number | Title | Issue Date |
| 8183937 | Integrated circuit frequency generator An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscil... | 05/22/2012 |
| 8125279 | System and method for reducing holdover duration A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of: timing information; frequency information; phase information; and combinations thereof. The device also has a LO error corrector comprising an input... | 02/28/2012 |
| 8120432 | System and method for selecting optimum local oscillator discipline source A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at least two inputs, each input c... | 02/21/2012 |
| 8089318 | Methods, algorithms, circuits, and systems for determining a reference clock frequency and/or locking a loop oscillator Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the refere... | 01/03/2012 |
| 8040193 | Oscillation adjusting circuit and method An oscillation tuning circuit is provided and includes a first circuit. The first circuit receives an input data stream with a known time interval, producing a first output signal having a first period, determines a first error signal representing a difference betwe... | 10/18/2011 |
| 8040194 | Frequency synthesizer using a phase-locked loop and single side band mixer A frequency synthesizer is built using a phase locked loop incorporating a single side band mixer in the input. The single side band mixer is preferably realized with digital logic and FETs, and the resulting frequency synthesizer simultaneously improves control ove... | 10/18/2011 |
| 7982545 | Transmission apparatus and method of switching phase lock reference frequency signal thereof An optical transmission apparatus according to the present invention connects a terminal apparatus side in which a transmission line is formed by, for example, SONET/SDH, and a WDM side in which a transmission line is formed by, for example, OTU3. The optical transm... | 07/19/2011 |
| 7961055 | PLL circuit and oscillator device A phase locked loop circuit includes an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator, and a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting cir... | 06/14/2011 |
| 7924099 | Method of establishing an oscillator clock signal A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wi... | 04/12/2011 |
| 7915962 | System and method for built in self test for timing module holdover Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at leas... | 03/29/2011 |
| 7907019 | Method and system for operating a MEMS scanner on a resonant mode frequency A method for operating a micro-electro-mechanical system (MEMS) scanner on a resonant mode frequency is provided. The method includes generating a drive signal for a MEMS scanner. A sensor signal is received from the MEMS scanner. The drive signal is compared to the... | 03/15/2011 |
| 7852160 | NCO based timebase recovery system and method for A/V decoder Systems and methods are disclosed for recovering a clock or time reference for A/V systems. One method comprises receiving at least one input time reference generated using a first clock and generating, using a second clock asynchronous to the first clock, at least ... | 12/14/2010 |
| 7786812 | Oscillators having reactance-adjustable frequency control In various embodiments, the invention provides a frequency controller to control and provide a stable resonant frequency of a clock generator and/or a timing and frequency reference. Such stability is provided over variations in a selected parameter such as temperat... | 08/31/2010 |
| 7777578 | Oscillator circuit, in particular for mobile radio An oscillator is disclosed that is tunable to discrete values, and includes a tuning element which can be connected via a switching device. A rectifier circuit is connected to the output of the oscillator and forms a clock signal from the oscillator signal. The osci... | 08/17/2010 |
| 7750742 | Enhanced all digital phase-locked loop and oscillation signal generation method thereof An All Digital PLL (ADPLL) and oscillation signal generation method using the ADPLL is provided for generating a spur-free oscillation signal by improving the frequency resolution of the ADPLL. An all digital phase-locked loop of the present invention includes a dig... | 07/06/2010 |
| 7719367 | Automatic frequency calibration Disclosed is a system and method for providing an oscillating signal of relatively precise frequency without using a signal provided by a crystal as a reference. Disclosed is a feedback oscillator circuit configured to output an oscillating signal having a frequency... | 05/18/2010 |
| 7675369 | Frequency hopping oscillator circuit A method for controlling a frequency output of a phase locked loop (PLL) is provided. The method includes providing digital control words to the PLL to discretely change at least one dividing factor within the PLL. The method further includes applying a time-varying... | 03/09/2010 |
| 7642862 | Digital phase locked loop A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisiti... | 01/05/2010 |
| 7619483 | Asynchronous phase acquisition unit with dithering A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital ... | 11/17/2009 |
| 7589595 | Distributing frequency references A correction processor connected to an oscillator uses precision timing signals propagated over a digital network to generate an error signal. IEEE-1588 time synchronization protocols produce precision time signals which are converted to precision interval signals. ... | 09/15/2009 |
| 7525392 | XtalClkChip: trimming-free crystal-free precision reference clock oscillator IC chip A XtalClkChip based on the application of hierarchical circuit and noise circuit design on the RF circuits of LC oscillation tank and the multi-phase fractional PLL are developed. The XtalClkChip combines both the XtalChip and multi-phase fractional PLL to provide t... | 04/28/2009 |
| 7436265 | Clock generator and clock generating method using delay locked loop Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locke... | 10/14/2008 |
| 7432770 | Signal transmission device The present invention provides a signal transmission device in which jitter occurring in a clock signal is eliminated. The signal transmission device has a construction in which a transmission end IC chip provided with a transmission part of a data signal and a rece... | 10/07/2008 |
| 7411461 | Frequency and/or phase lock loops with beat frequency estimation A control loop (10) for producing an output signal with a stable nominal frequency is provided. The control loop includes inputs for reference (11) and oscillator (25) output signals, a beat frequency generator (12) for producing a signal... | 08/12/2008 |
| 7394328 | Oscillator circuit and test apparatus An oscillator circuit that generates an oscillation signal is provided. The oscillator circuit includes an oscillator that generates the oscillation signal based on positive feedback of a signal, a synchronization signal generating section that generates a compulsor... | 07/01/2008 |
| 7382202 | Apparatus and method to provide a local oscillator signal from a digital representation An apparatus provides a local oscillator signal based on a selected channel of an RF input signal. For example, the apparatus can set a frequency of the local oscillator signal based on the selected channel. Digital circuitry can be used to generate the local oscill... | 06/03/2008 |
| 7378918 | Two-point modulation type phase modulation apparatus, polar modulation transmission apparatus, wireless transmission apparatus and wireless communication apparatus There provides a two-point modulation phase modulation apparatus capable of obtaining an RF phase modulation signal of superior modulation precision with low power consumption and a simple configuration even in the event of inputting a wide band baseband modulation ... | 05/27/2008 |
| 7375591 | Robust false locking prevention in referenceless frequency acquisition An output of an oscillator of a phase-locked loop is swept across a predetermined frequency range by varying control settings associated with the oscillator. A plurality of control settings that cause the oscillator to lock or falsely lock to the timing of an input ... | 05/20/2008 |
| 7375592 | System and method for maintaining an accurate frequency on a voltage controlled oscillator A method for phase-locking a voltage controlled oscillator is disclosed. The method comprises receiving, at a phase detector, a phase input signal and a phase feedback signal from the voltage controlled oscillator; measuring a pulse width property of an error signal... | 05/20/2008 |
| 7365565 | Programmable system on a chip for power-supply voltage and current monitoring and control A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip... | 04/29/2008 |
| 7362185 | Analog based, state machine controlled, frequency smooth switching method for frequency timing generators A method and circuit for performing switching in a frequency timing generator is described. The method includes detecting a request for a new value for a feedback counter or an reference counter, upon which a loading operation is synchronized for the appropriate cou... | 04/22/2008 |
| 7363013 | Phase lock loop applying in wireless communication system and method thereof A phase lock loop receives a baseband signal which has an input frequency, and modulating the baseband signal to be a corresponding RF signal which has a predetermined transmission frequency for transmitting. The phase lock loop comprises a programmable divider, a m... | 04/22/2008 |
| 7355462 | Phase lock loop and method for operating the same A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for receiving upward and downward adjustment signals, respectively. The digital... | 04/08/2008 |
| 7355486 | Current controlled oscillation device and method having wide frequency range A current controlled, phase locked loop device includes a phase detector configured to compare a reference frequency to an output frequency of a current controlled oscillator (ICO), a charge pump coupled to the phase detector and a low pass filter coupled to the cha... | 04/08/2008 |
| 7352206 | Integrated circuit device having state-saving and initialization feature An integrated circuit device has a state-saving feature and includes a programmable logic block, I/O pads, a dedicated register, at least one volatile memory block, a non-volatile memory block, a condition-sensing circuit for detecting at least one condition, A cont... | 04/01/2008 |
| 7352297 | Method and apparatus for efficient implementation of digital filter with thermometer-code-like output A technique is disclosed for processing a binary coded signal to generate a thermometer coded signal. Such technique includes the following steps. A binary coded input signal is obtained. A binary arithmetic operation is performed on a least significant bit (LSB) po... | 04/01/2008 |
| 7353011 | Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitanc... | 04/01/2008 |
| 7342528 | Circuit and method for reducing electromagnetic interference A spread spectrum system having a self-oscillating delay-line digital pulse width modulator and a method for mitigating electromagnetic interference. The spread spectrum system has a pseudo-random pattern generator connected to a digital-to-analog converter, which i... | 03/11/2008 |
| 7336548 | Clock generating circuit with multiple modes of operation A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by... | 02/26/2008 |
| 7336748 | DDS circuit with arbitrary frequency control clock A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock... | 02/26/2008 |
