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Pizza Pie With Concentric Rings of Crust
A pizza mold for forming a plurality of concentric raised ridges of dough (i.e., crust) on the surface of a pizza pie.
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| Number | Title | Issue Date |
| 7973606 | Fractional-N frequency synthesizer and method thereof The present relates to a fractional-N frequency synthesizer improving noise characteristics and a method thereof. The fractional-N frequency synthesizer includes a reference oscillator that generates a reference frequency signal; a sigma-delta modulator that generat... | 07/05/2011 |
| 7956694 | Phase controlled dimmer using a narrow band quadrature demodulator A modified Costas control loop (80) using switched analog low pass filters (R2, C1, C2) (R3, C3, C4) and rectangular to polar conversion (341) computes an angular phase reference error that is processed by a di... | 06/07/2011 |
| 7636018 | Phase locked loop with phase shifted input In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to th... | 12/22/2009 |
| 7557663 | Digital PLL for a system-on-chip for digital control of electronic power devices A digital phase locked loop (DPLL) comprising a digitally implemented voltage controlled oscillator (VCO) for producing a VCO feedback signal, a phase error counter which includes a digital phase-frequency detector for producing a first phase error signal, a quadrat... | 07/07/2009 |
| 7409029 | Transmission device for automatically set an optimal point for a signal decision making There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynami... | 08/05/2008 |
| 7394321 | Quadrature VCO system and method A low-power quadrature generator is provided for accurately generating in-phase signals and quadrature signals. ... | 07/01/2008 |
| 7363013 | Phase lock loop applying in wireless communication system and method thereof A phase lock loop receives a baseband signal which has an input frequency, and modulating the baseband signal to be a corresponding RF signal which has a predetermined transmission frequency for transmitting. The phase lock loop comprises a programmable divider, a m... | 04/22/2008 |
| 7362826 | Receiver including an oscillation circuit for generating an image rejection calibration tone A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desir... | 04/22/2008 |
| 7358782 | Frequency divider and associated methods The present invention relates to frequency dividers. The frequency divider comprises an input, a counter, a first comparator, an interconnect, and an output. The counter has a counter reset port and is configured to receive a clock signal from the input and to produ... | 04/15/2008 |
| 7356106 | Clock and data recovery circuit A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects frequency difference between the output signals of the PD and QP detector and... | 04/08/2008 |
| 7336938 | Phase-alternating mixer with alias and harmonic rejection Rejection of local oscillator alias response is provided in a mixing circuit by (1) a switching mixer producing an output that changes at least twice between two states (e.g., high-low-high or low-high-low) during each local oscillator period, and (2) a charge integ... | 02/26/2008 |
| 7323943 | PLL circuit with deadlock detection circuit Disclosed is a PLL circuit including a deadlock detection circuit includes a counter circuit for counting a clock signal. In a deadlock state, the deadlock detection circuit outputs a deadlock detection signal responsive to an output signal from the counter circuit ... | 01/29/2008 |
| 7312669 | Oscillation circuit An oscillation circuit for generating two oscillation signals having a phase difference of 90° by using an LC oscillator has a disadvantage for integration. Therefore, a differential type ring oscillator comprising interpolation type delay circuits of four stages i... | 12/25/2007 |
| 7298217 | Phased array radar systems and subassemblies thereof A phase shifter is fed an input signal having a frequency f. A coupler is included fed by the input signal. The coupler has a pair of output terminals for providing a pair of signals having the frequency f and having a relative phase shift difference of mπ/2 radian... | 11/20/2007 |
| 7295640 | Phase detector A phase detector has a reference signal input for a reference signal and a detector input for a signal to be evaluated. A memory unit is connected to the detector input and stores a state of the signal to be evaluated at a storage instant. An evaluation unit is conn... | 11/13/2007 |
| 7289542 | Method for operating a PLL frequency synthesis circuit In a method for operating a PLL frequency synthesis circuit, the circuit is in an active state and synthesizes a first output frequency during a first data transmission period. The circuit is likewise active and synthesizes a second, different output frequency durin... | 10/30/2007 |
| 7272203 | Data-directed frequency-and-phase lock loop for decoding an offset-QAM modulated signal having a pilot A data-and-pilot directed frequency-and-phase lock loop for an offset-QAM modulated signal having a pilot signal comprising a pilot acquisition loop and a pair of data-directed acquisition loops. The pilot is extracted from the main signal by a pilot filter, then us... | 09/18/2007 |
| 7265637 | Startup/yank circuit for self-biased phase-locked loops An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, ... | 09/04/2007 |
| 7263344 | Method for reducing IM2 noise in a down conversion circuit The present invention relates generally to communications, and more specifically to a method and apparatus for minimizing DC offset and second-order modulation products (IM2 noise) while demodulating RF signals. The principle of the invention can be applied to diffe... | 08/28/2007 |
| 7256629 | Phase-locked loops A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module fu... | 08/14/2007 |
| 7215703 | Digital calculation received signal strength indication Digital calculation of an RSSI value begins by digitally calculating a magnitude of a signal (e.g., a received RF signal or representation thereof). The process then continues by filtering the magnitude of the signal to produce a filtered magnitude signal. The proce... | 05/08/2007 |
| 7209532 | Phase lock loop and method for coded waveforms A communication system from maintaining synchronization includes a communication signal comprising a carrier and a data signal that is sent from a transmitter to a receiver which includes a phase lock loop. The receiver compares the output of a Viterbi decoder with ... | 04/24/2007 |
| 7209008 | Multiple output phase-locked loop (PLL) using a single voltage controlled oscillator (VCO) Phase-locked loop (PLL) methods and apparatus are described for generating multiple output clocks synchronized to different frequencies of multiple input signals, wherein the multiple-output PLL employs a single voltage controlled oscillator (VCO). In an embodiment,... | 04/24/2007 |
| 7180933 | Squelch circuitry for high speed high frequency operation A squelch circuit for operating at high speed and at high frequencies includes a squelch input unit, a low swing pre-amplifier and a sampling and decision circuit. The squelch input unit pre-processes the positive and negative signals of an input signal to generate ... | 02/20/2007 |
| 7180344 | Phase locked loop and method for trimming a loop filter The invention includes a phase locked loop which has a voltage-controlled oscillator, a phase comparator and a charge pump. The charge pump is coupled to a setting input of the voltage-controlled oscillator via a loop filter. A feedback input of the phase comparator... | 02/20/2007 |
| 7138839 | Phase-locked loops A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control current and varies the control current in proportion to an inverse of N squared. N is the ratio of the output frequency of the PLL system to the reference fr... | 11/21/2006 |
| 7136445 | Phase tracker for linearly modulated signal A method is disclosed for tracking the phase of a received phase-modulated carrier carrying a sequence of symbols represented by phase jumps in a low signal-to-noise ratio environment. An input sequence of symbols stored in a delay line. The phase of a current symbo... | 11/14/2006 |
| 7116953 | Local oscillator using I/Q mismatch compensating circuit through LO path receiver using thereof A local oscillator provides an in-phase local oscillating signal and quadrature-phase signal to first and second mixers outputting an input signal with a mixed in-phase local oscillating signal and quadrature-phase local oscillating signal, respectively. The oscilla... | 10/03/2006 |
| 7116176 | Multiple synthesized clocks from a single clock source A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signal... | 10/03/2006 |
| 7102448 | Phase frequency detector used in phase locked loop A phase frequency detector used in a phase locked loop includes a phase error detecting unit for outputting phase error signals according to a phase error between a first input signal and a second input signal, and a reset unit coupled to the phase error detecting u... | 09/05/2006 |
| 7102450 | Method and apparatus for providing clock signals at different locations with minimal clock skew A tapped phase shift ring oscillator may be used to provide multiple clock signals having variable phase delays. Phase delays may be selected to compensate for clock skews at different locations on high speed chips, or to provide clock signals having specific, desir... | 09/05/2006 |
| 7095289 | Yank detection circuit for self-biased phase locked loops An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, ... | 08/22/2006 |
| 7092458 | Carrier recovery circuit and lock detection circuit for mixed PSK signals A BPSK phase detection unit assumes that an input signal is a BPSK modulated signal in detecting a phase error of a recovered carrier and an 8PSK phase detection unit assumes that the input signal is an 8PSK modulated signal in detecting the phase error of the recov... | 08/15/2006 |
| 7092475 | Phase-frequency detector with linear phase error gain near and during phase-lock in delta sigma phase-locked loop A phase-frequency detector (PFD) having substantially linear phase error gain within a predetermined phase error range centered about zero phase error when used in a delta sigma phase-locked loop (PLL). The output signals (e.g., charge pump control signals), which a... | 08/15/2006 |
| 7075957 | Controlling an optical source using a beat frequency An apparatus and method of controlling an optical signal includes superimposing at least one optical reference signal and the optical signal to obtain at least one interference signal having an actual beat frequency, and pre-selecting one or more of the at least one... | 07/11/2006 |
| 7061997 | Method and apparatus for fine frequency synchronization in multi-carrier demodulation systems A method and an apparatus relating to a fine frequency synchronization compensating for a carrier frequency deviation from an oscillator frequency in a multi-carrier demodulation system of the type capable of carrying out a differential phase decoding of multi-carri... | 06/13/2006 |
| 7061330 | Oscillator including phase frequency detectors for detecting a phase difference between two input signals and outputting a control command signal An oscillator includes phase frequency detectors, each detecting the phase difference between two input signals (output signal and external reference signal) and outputting a control command signal for controlling the output signal to achieve a desired frequency on ... | 06/13/2006 |
| 7061276 | Digital phase detector A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal ... | 06/13/2006 |
| 7038507 | Frequency synthesizer having PLL with an analog phase detector A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes a phase locked loop (PLL) having an analog mixer phase detector and an auxiliary digital frequency detector coupled to the phase locked loop. The PLL may include a ... | 05/02/2006 |
| 7034622 | Phase-locked loop circuit and data reproduction apparatus This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functi... | 04/25/2006 |
